Transistor Level Modeling for Analog/RF IC Design

Author:   Wladyslaw Grabinski ,  Bart Nauwelaers ,  Dominique Schreurs
Publisher:   Springer-Verlag New York Inc.
Edition:   2006 ed.
ISBN:  

9781402045554


Pages:   294
Publication Date:   22 March 2006
Format:   Hardback
Availability:   In Print   Availability explained
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Transistor Level Modeling for Analog/RF IC Design


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Overview

Among many great inventions made in the 20th century, electronic circuits, which later evolved into integrated circuits, are probably the biggest, when considering their contribution to human society. Entering the 21st century, the importance of integrated circuits has increased even more. In fact, without the help of integrated circuits, recent high-technology society with the internet, cellular phone, car navigation, digital camera, and robot would never have been realized. Nowadays, integrated circuits are indispensable for almost every activity of our society. One of the critical issues for the fabrication of integrated circuits has been the precise design of the high-speed or high-frequency operation of circuits with huge number of components. It is quite natural to predict the circuit operation by computer calculation, and there have been three waves for this, at 15-year intervals. The ?rst wave came at the beginning of the 1970s when LSIs (Large Scale Integrated circuits) with more than 1000 components had just been int- duced into the market. A mainframe computer was used for the simulation, and each semiconductor company used its own proprietary simulators and device models. However, the capability of the computer and accuracy of the model were far from satisfactory, and there are many cases of the necessity of circuit re-design after evaluation of the ?rst chip. The second wave hit us in the middle of 1980s, when the EWS (Engine- ing Work Station) was introduced for use by designers.

Full Product Details

Author:   Wladyslaw Grabinski ,  Bart Nauwelaers ,  Dominique Schreurs
Publisher:   Springer-Verlag New York Inc.
Imprint:   Springer-Verlag New York Inc.
Edition:   2006 ed.
Dimensions:   Width: 15.50cm , Height: 1.90cm , Length: 23.50cm
Weight:   1.340kg
ISBN:  

9781402045554


ISBN 10:   1402045557
Pages:   294
Publication Date:   22 March 2006
Audience:   Professional and scholarly ,  Professional & Vocational
Format:   Hardback
Publisher's Status:   Active
Availability:   In Print   Availability explained
This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us.

Table of Contents

2/3-D process and device simulation. An effective tool for better understanding of internal behavior of semiconductor structures.- PSP: An advanced surface-potential-based MOSFET model.- EKV3.0: An advanced charge based MOS transistor model.A design-oriented MOS transistor compact model.- Modelling using high-frequency measurements.- Empirical FET models.- Modeling the SOI MOSFET nonlinearities. An empirical approach.- Circuit level RF modeling and design.- On incorporating parasitic quantum effects in classical circuit simulations.- Compact modeling of the MOSFET in VHDL-AMS.- Compact modeling in Verilog-A.

Reviews

A comprehensive book on state of the art emerging MOSFET models for the design and simulation of analog, digital or RF Integrated Circuits. <br>Narain Arora, Cadence Design Systems, California, USA <p> This book covers modern topics in semiconductor TCAD, circuit simulation, compact models, RF modeling, etc. which are hard to find together anywhere else. <br>Peter Bendix, Xpedion Design Systems, California, USA


A comprehensive book on state of the art emerging MOSFET models for the design and simulation of analog, digital or RF Integrated Circuits. Narain Arora, Cadence Design Systems, California, USA This book covers modern topics in semiconductor TCAD, circuit simulation, compact models, RF modeling, etc. which are hard to find together anywhere else. Peter Bendix, Xpedion Design Systems, California, USA


Author Information

Dr. Grabinski, Dr. Nauwelaers and Dr. Scheurs organized the MOS-Modeling workshop at the European Solid-State Devices Conference (ESSDERC) in 2004, and due to popular request will do again at ESSDERC 2005 in Grenoble. Dr. Grabinski is in industry, at Freescale Semiconductor, while Dr. Nauwelaers and Dr. Schreurs are in academia.

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