RISC-V System-On-Chip Design

Author:   David Harris (Associate Professor of Engineering, Harvey Mudd College, Claremont, CA, USA) ,  James Stine (School of Electrical and Computer Engineering, Oklahoma State University, Stillwater, OK, USA) ,  Sarah Harris (Assistant Professor of Engineering, Harvey Mudd College, Claremont, CA, USA) ,  Rose Thompson
Publisher:   Elsevier Science & Technology
ISBN:  

9780323994989


Pages:   600
Publication Date:   01 July 2025
Format:   Paperback
Availability:   In Print   Availability explained
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RISC-V System-On-Chip Design


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Overview

RISC-V Microprocessor System-On-Chip Design is written to be accessible to an advanced undergraduate audience with limited background. It explains concepts from operating systems, VLSI, and memory systems as necessary, and High school mathematics is sufficient preparation for most of the book, although the floating point and division chapters will be primarily of interest to those with a curiosity about computer arithmetic. Like Harris and Harris’s Digital Design and Computer Architecture textbooks, this book will appeal to students with easy-to-read and complete explanations, sidebars, and occasional humor and cartoons. It comes with an open-source implementation and will include end-of-chapter problems to extend the RISC-V processor in various ways. Ancillary materials include a GitHub repository with complete open-source SystemVerilog code, validation code in C and assembly language, and code for benchmarking and booting Linux.

Full Product Details

Author:   David Harris (Associate Professor of Engineering, Harvey Mudd College, Claremont, CA, USA) ,  James Stine (School of Electrical and Computer Engineering, Oklahoma State University, Stillwater, OK, USA) ,  Sarah Harris (Assistant Professor of Engineering, Harvey Mudd College, Claremont, CA, USA) ,  Rose Thompson
Publisher:   Elsevier Science & Technology
Imprint:   Morgan Kaufmann
Weight:   0.450kg
ISBN:  

9780323994989


ISBN 10:   0323994989
Pages:   600
Publication Date:   01 July 2025
Audience:   College/higher education ,  Tertiary & Higher Education
Format:   Paperback
Publisher's Status:   Active
Availability:   In Print   Availability explained
This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us.

Table of Contents

1. Introduction Part 1: RISC-V Architecture 2. RISC-V Architecture 3. Assembly Language Programming 4. C Programming Part 2: RISC-V Microarchitecture 5. Microarchitecture Overview 6. Survey of Microarchitectures 7. RISC-V Pipelined Microarchitecture 8. Privileged Operations 9. AHB Interface 10. Virtual Memory 11. Branch Prediction 12. RISC-V Superscalar Microarchitecture 13. RISC-V Threaded Microarchitecture 14. Extensions: Compressed Instructions 15. Extensions: Multiplication and Division 16. Extensions: Floating Point 17. Extensions: Atomic Operations 18. More Bus Interfaces 19. Peripherals 20. Multicore 21. SIMD 22. Vector 23. Bit Manipulation 24. Crypto Part 3: Validation 25. Logic Verification 26. Performance Validation: Benchmarking 27. Linux Boot Part 4: Implementation 28. FPGA Implementation 29. CMOS for Microarchitects 30. CMOS Implementation 31. Silicon Debug

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Author Information

David Harris is the Harvey S. Mudd Professor of Engineering Design at Harvey Mudd College. He received his Ph.D. in electrical engineering from Stanford University and his M.Eng. in electrical engineering and computer science from MIT. Before attending Stanford, he worked at Intel as a logic and circuit designer on the Itanium and Pentium II processors. Since then, he has consulted at Sun Microsystems, Hewlett-Packard, Broadcom, and other design companies. David holds more than a dozen patents and is the author of three other textbooks on chip design, as well as many Southern California hiking guidebooks. When he is not working, he enjoys hiking, flying, and making things with his three sons. James Stine is the Edward Joullian Professor of Engineering at Oklahoma State University. His area of research is in computer arithmetic, memory architectures, and Electronic Design Automation (EDA) design flow. He is the author of numerous articles on optimization of architectures for use with computer arithmetic as well as interfacing to memory architectures. He is the author of three texts: Digital Datapath Computer Arithmetic with Verilog, Adder Architectures for VLSI Implementations and System on Chip Design Flow and Standard-Cell Library. Sarah L. Harris is an Assistant Professor of Engineering at Harvey Mudd College. She received her Ph.D. and M.S. in Electrical Engineering from Stanford University. Before attending Stanford, she received a B.S. in Electrical and Computer Engineering from Brigham Young University. Sarah has also worked with Hewlett-Packard, the San Diego Supercomputer Center, Nvidia, and Microsoft Research in Beijing. Sarah loves teaching, exploring and developing new technologies, traveling, wind surfing, rock climbing, and playing the guitar. Her recent exploits include researching sketching interfaces for digital circuit design, acting as a science correspondent for a National Public Radio affiliate, and learning how to kite surf. She speaks four languages and looks forward to learning more in the near future.

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