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OverviewThe market for consumer electronics is characterized by rapidly growing complexities of applications and decreasing market window opportunities. A key concept for coping with such requirements is the reuse of system components. Embedding programmable processors into VLSI systems facilitates reuse and offers a high degree of flexibility. The use of embedded processors, however, poses challenges for software compilers, because real-time constraints and limited silicon area for program memories demand extremely efficient machine code. Additionally there is a need for flexible, retargetable compilers which explore the mutual dependence between processor architectures and program execution speed. Current compiler technology does not meet these demands, particularly the area of DSP where application-specific processors are predominant. As a consequence, the largest part of DSP software is still developed manually at assembly language level. Recent research efforts, located at the intersection of software and hardware design, aim at eliminating this bottleneck. Retargetable Code Generation for Digital Signal Processors outlines the new role of compilers in hardware/software codesign of embedded systems, and it describes the state-of-the-art in the area of retargetable code generation and optimization for embedded DSPs. It presents novel concepts and algorithmic solutions, which achieve both retargetability and high code quality. In contrast to approaches taken in classical compiler construction, emphasis is put on effective code optimization instead of high compilation speed. The usefulness of the proposed techniques is demonstrated for real-life architectures. Retargetable Code Generation for Digital Signal Processors, with a foreword by Peter Marwedel, is the first contribution to this area, that presents an integrated solution for retargetable DSP compilers. It covers the whole compilation process, including target processor modelling, intermediate code generation, code selection, register allocation, scheduling and optimization for parallelism. It will be of interest to researchers, senior design engineers and CAD managers both in academia and industry. Full Product DetailsAuthor: Rainer LeupersPublisher: Springer-Verlag New York Inc. Imprint: Springer-Verlag New York Inc. Edition: Softcover reprint of hardcover 1st ed. 1997 Dimensions: Width: 15.50cm , Height: 1.20cm , Length: 23.50cm Weight: 0.454kg ISBN: 9781441951816ISBN 10: 1441951814 Pages: 210 Publication Date: 07 December 2010 Audience: College/higher education , Professional and scholarly , Postgraduate, Research & Scholarly , Professional & Vocational Format: Paperback Publisher's Status: Active Availability: Manufactured on demand  We will order this item for you from a manufactured on demand supplier. Table of Contents1 Introduction.- 2 Processor Modelling.- 3 Instruction-Set Extraction.- 4 Code Generation.- 5 Instruction-Level Parallelism.- 6 The Record Compiler.- 7 Conclusions.- References.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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