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OverviewUntil the 1990s, the reduction of the minimum feature sizes used to fabricate in- grated circuits, called “scaling”, has highlighted serious advantages as integration density, speed, power consumption, functionality and cost. Direct consequence was the decrease of cost-per-function, so the electronic productivity has largely progressed in this period. Another usually cited trend is the evolution of the in- gration density as expressed by the well-know Moore’s Law in 1975: the number of devices per chip doubles every 2 years. This evolution has allowed improving signi?cantly the circuit complexity, offering a great computing power in the case of microprocessor, for example. However, since few years, signi?cant issues appeared such as the increase of the circuit heating, device complexity, variability and dif?culties to improve the integration density. These new trends generate an important growth in development and production costs. Though is it, since 40 years, the evolution of the microelectronics always f- lowed the Moore’s law and each dif?culty has found a solution. Full Product DetailsAuthor: Amara Amara , Olivier RozeauPublisher: Springer Imprint: Springer Edition: Softcover reprint of hardcover 1st ed. 2009 Dimensions: Width: 15.50cm , Height: 1.10cm , Length: 23.50cm Weight: 0.454kg ISBN: 9789048181087ISBN 10: 9048181089 Pages: 211 Publication Date: 19 October 2010 Audience: Professional and scholarly , Professional & Vocational Format: Paperback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of ContentsIntroduction. 1 Multiple Gate Technologies; Thierry Poiroux, Maud Vinet and Simon Deleonibus. 1.1 Introduction. 1.2. Advantages of multiple gate technologies. 1.3. Planar double gate technologies. 1.4. Non planar multiple gate technologies. 1.5. Conclusions and perspectives. References. 2 Compact Modeling of Independent Double-Gate Mosfet: a Physical Approach; Daniela Munteanu and Jean-Luc Autran. 2.1. Introduction. 2.2. Drift-diffusion Drain current modeling. 2.3. Ballistic current in the subthreshold regime. 2.4. Conclusion. References. 3 Compact Modeling of Double Gate MOSFET for IC Design; Marina Reyboz, Olivier Rozeau and Thierry Poiroux. 3.1. Introduction. 3.2. Modeling of Independent Gate MOSFET With Independent Driven Gates. 3.3. Long channel IDG MOSFET Threshold voltage based model. 3.4. Short channel effects. 3.5. Conclusion. References. 4 Low Frequency Noise in Double-Gate SOI CMOS Devices; Jalal Jomaah and Gérard Ghibaudo. 4.1. Introduction. 4.2. Low Frequency Noise Analysis. 4.3. Results and Discussions. 4.4. Conclusion. References. 5 Analog Circuit Design; Philippe Freitas, David Navarro, Ian O'Connor, Gérard Billiot, Hervé Lapuyade and Jean-Baptiste Begueret. 5.1. Double Gate MOSFET In Analog Design. 5.2. Current Mirrors. 5.3. Differential Pairs. 5.4. Low Voltage OTAS. 5.5. High Speed Comparators. 5.6. Conclusion. References. 6 Logic Circuit Design With DGMOS Devices; Ian O'Connor, Ilham Hassoune, Xi Yang and David Navarro. 6.1. DGMOS characteristics and impact on digital design. 6.2. Standard cells using DGMOS. 6.3. Ultra Low Power full-adder using Double gate SOI devices. 6.4. DGMOS DEVICE based reconfigurable cells. References. 7 SRAM CircuitDesign; Bastien Giraud, Olivier Thomas, Amara Amara, Andrei Vladimirescu and Marc Belleville. 7.1. Introduction. 7.2. SRAM memories. 7.3. Double gate 6T SRAM memories. 7.4. Double gate 4T & 5T SRAM memories. References. Conclusion. Appendix. Index.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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