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OverviewThis text introduces the concepts of analogue multirate signal processing for the efficient implementation of two-dimensional (2-D) filtering in integrated circuit form, particularly from the viewpoints of silicon area and power dissipation. New 2-D switched-capacitor (SC) networks and design techniques are presented, both with finite impulse response (FIR) and infinite impulse response (IIR) with separable denominator polynomial, which offer simpler and more systematic synthesis procedures than currently available design techniques for 2-D analogue filters. Since they are in the discrete-time domain, the book can be also referred to the digital multirate signal processing. A 2-D SC image processor that realizes both (2 x 2)nd-order Butterworth lowpass and highpass filtering functions for video image signals was realized as a prototype integrated circuit implemented in 1.0-mm CMOS technology. Full Product DetailsAuthor: Wang Ping , José E. FrancaPublisher: Springer Imprint: Springer Edition: 1998 ed. Volume: 427 Dimensions: Width: 15.50cm , Height: 0.90cm , Length: 23.50cm Weight: 0.870kg ISBN: 9780792380511ISBN 10: 0792380517 Pages: 124 Publication Date: 30 November 1997 Audience: College/higher education , Professional and scholarly , Undergraduate , Postgraduate, Research & Scholarly Format: Hardback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of Contents1 Introduction.- 1.1 Introductory Remarks.- 1.2 Book Outline.- References.- 2 2-D Signals and Filtering Systems.- 2.1 Introduction.- 2.2 2-D Signals.- 2.3 2-D Image Filtering Systems.- 2.4 Hardware Implementation of 2-D Filters.- 2.5 Application Examples of 2-D Filter Systems.- 2.6 Summary.- References.- 3 Fundamental Aspects of 2-D Decimation Filters.- 3.1 Introduction.- 3.2 1-D Decimation.- 3.3 2-D Decimation.- 3.4 Delay-Line Memory Requirements for 2-D Filters.- 3.5 Summary.- References.- 4 Polyphase-Coefficient Structures for 2-D Decimation Filters.- 4.1 Introduction.- 4.2 Modified 1-D Decimation Polyphase Structures.- 4.3 Polyphase-Coefficient Structures for 2-D Decimation Filters.- 4.4 Summary.- References.- 5 SC Architectures for 2-D Decimation Filters in Polyphase-Coefficient Form.- 5.1 Introduction.- 5.2 SC Building Blocks.- 5.3 SC Architectures with 2-D Polyphase-Coefficients.- 5.4 Design Example of an FIR 2-D Decimation Filter.- 5.5 Design Example of an IIR 2-D Decimation Filter.- 5.6 Summary.- References.- 6 A Real-Time 2-D Analog Multirate Image Processor in 1.0-µm CMOS Technology.- 6.1 Introduction.- 6.2 2-D Multirate Filter Design.- 6.3 SC Horizontal Decimation Filter.- 6.4 SC Vertical Filter and Associated Delay-Line Memory Blocks.- 6.5 Integrated Circuit Implementation.- 6.6 Experimental Characterization.- 6.7 Summary.- References.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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