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OverviewThe exponential scaling of feature sizes in semiconductor technologies has side-effects on layout optimization, related to effects such as interconnect delay, noise, crosstalk, signal integrity, parasitics effects and power dissipation, that invalidate the assumptions that form the basis of previous design methodologies and tools. This book is intended to sample the most important, contemporary and advanced layout optimization problems emerging with the advent of very deep submicron technologies in semiconductor processing. A reference work for graduate students, senior undergraduates and researchers. Full Product DetailsAuthor: Bing Lu , Ding-Zhu Du , S. SapatnekarPublisher: Springer-Verlag New York Inc. Imprint: Springer-Verlag New York Inc. Edition: 2001 ed. Volume: 8 Dimensions: Width: 15.50cm , Height: 1.70cm , Length: 23.50cm Weight: 1.320kg ISBN: 9781402000898ISBN 10: 1402000898 Pages: 288 Publication Date: 31 December 2001 Audience: College/higher education , Professional and scholarly , Undergraduate , Postgraduate, Research & Scholarly Format: Hardback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of Contents1. Integrated Floorplanning and Interconnect Planning.- 2. Interconnect Planning.- 3. Modern Standard-cell Placement Techniques.- 4. Non-Hanan Optimization for Global VLSI Interconnect.- 5. Techniques for Timing-Driven Routing.- 6. Interconnect Modeling and Design with Consideration of Inductance.- 7. Modeling and Characterization of IC Interconnects and Packagings for the Signal Intergrity Verification on High-Performance VLSI Circuits.- 8. Tradeoffs in Digital Binary Adder Design: the Effects of Floorplanning, Number of Levels of Metals, and Supply Voltage on Performance and Area.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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