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OverviewThis book describes design techniques that can be used to mitigate crosstalk in high-speed I/O circuits. The focus of the book is in developing compact and low power integrated circuits for crosstalk cancellation, inter-symbol interference (ISI) mitigation and improved bit error rates (BER) at higher speeds. This book is one of the first to discuss in detail the problem of crosstalk and ISI mitigation encountered as data rates have continued beyond 10Gb/s. Readers will learn to avoid the data performance cliff, with circuits and design techniques described for novel, low power crosstalk cancellation methods that are easily combined with current ISI mitigation architectures. Full Product DetailsAuthor: Taehyoun Oh , Ramesh HarjaniPublisher: Springer-Verlag New York Inc. Imprint: Springer-Verlag New York Inc. Edition: Softcover reprint of the original 1st ed. 2014 Dimensions: Width: 15.50cm , Height: 0.50cm , Length: 23.50cm Weight: 0.454kg ISBN: 9781493954223ISBN 10: 1493954229 Pages: 89 Publication Date: 23 August 2016 Audience: Professional and scholarly , Professional & Vocational Format: Paperback Publisher's Status: Active Availability: Manufactured on demand  We will order this item for you from a manufactured on demand supplier. Table of ContentsIntroduction.- 2x6 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Scheme in 130 nm CMOS Process.- 4x12 Gb/s MIMO Crosstalk Cancellation and Signal Reutilization Receiver in 65 nm CMOS Process.- Adaptive XTCR, AGC, and Adaptive DFE Loop.- Research Summary & Contributions.- References.- Appendix A: Noise Analysis.- Appendix B: Issues of Applying Consecutive 2x2 XTCR on Multi-Lane I/Os (≥ 4).- Appendix C: Transmitter-Side Discrete-Time FIR XTC Filter versus Receiver-Side Analog-IIR XTC Filter.- Appendix D: Line Mismatch Sensitivity.- Appendix E: Input Matching for 4x4 XTCR Receiver Test Bench.- Appendix F: Bandwidth Improvement by Technology Scaling.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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