Design of Cost-Efficient Interconnect Processing Units: Spidergon Stnoc

Author:   Miltos D Grammatikakis ,  Marcello Coppola ,  Riccardo Locatelli ,  Giuseppe Maruccia
Publisher:   CRC Press
ISBN:  

9786611863142


Pages:   293
Publication Date:   01 January 2009
Format:   Electronic book text
Availability:   Out of stock   Availability explained
The supplier is temporarily out of stock of this item. It will be ordered for you on backorder and shipped when it becomes available.

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Design of Cost-Efficient Interconnect Processing Units: Spidergon Stnoc


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Overview

This book presents streamlined design solutions specifically for NoC. To solve critical network-on-chip (Noe architecture and design problems related to structure, performance and modularity, engineers generally rely on guidance from the abundance of literature about better-understood system-level interconnection networks. However, on-chip networks present several distinct challenges that require novel and specialized solutions not found in the tried-and-true system-level techniques.A Balanced Analysis of NoC Architecture - As the first detailed description of the commercial Spidergon STNoC architecture, Design of Cost-Efficient Interconnect Processing Units: Spidergon STNoC examines the highly regarded, cost-cutting technology that is set to replace well-known shared bus architectures, such as STBus, for demanding multiprocessor system-on-chip (Soe applications. Employing a balanced, well-organized structure, simple teaching methods, numerous illustrations, and easy-to-understand examples, the authors explain: how the SoC and NoC technology works why developers designed it the way they did the system-level design methodology and tools used to configure the Spidergon STNoC architecture differences in cost structure between NoCs and system-level networks.From professionals in computer sciences, electrical engineering, and other related fields, to semiconductor vendors and investors - all readers will appreciate the encyclopedic treatment of background NoC information ranging from CMPs to the basics of interconnection networks. The text introduces innovative system-level design methodology and tools for efficient design space exploration and topology selection. It also provides a wealth of key theoretical and practical MPSoC and NoC topics, such as technological deep sub-micron effects, homogeneous and heterogeneous processor architectures, multicore SoC, interconnect processing units, generic NoC components, and embeddings of common communication patterns.It is an arsenal of practical learning tools at your disposal.

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Author:   Miltos D Grammatikakis ,  Marcello Coppola ,  Riccardo Locatelli ,  Giuseppe Maruccia
Publisher:   CRC Press
Imprint:   CRC Press
ISBN:  

9786611863142


ISBN 10:   6611863141
Pages:   293
Publication Date:   01 January 2009
Audience:   General/trade ,  General
Format:   Electronic book text
Publisher's Status:   Active
Availability:   Out of stock   Availability explained
The supplier is temporarily out of stock of this item. It will be ordered for you on backorder and shipped when it becomes available.

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