Deep Reinforcement Learning Processor Design for Mobile Applications

Author:   Juhyoung Lee ,  Hoi-Jun Yoo
Publisher:   Springer International Publishing AG
Edition:   1st ed. 2023
ISBN:  

9783031367922


Pages:   101
Publication Date:   15 August 2023
Format:   Hardback
Availability:   Manufactured on demand   Availability explained
We will order this item for you from a manufactured on demand supplier.

Our Price $343.17 Quantity:  
Add to Cart

Share |

Deep Reinforcement Learning Processor Design for Mobile Applications


Add your own review!

Overview

This book discusses the acceleration of deep reinforcement learning (DRL), which may be the next step in the burst success of artificial intelligence (AI). The authors address acceleration systems which enable DRL on area-limited & battery-limited mobile devices. Methods are described that enable DRL optimization at the algorithm-, architecture-, and circuit-levels of abstraction.

Full Product Details

Author:   Juhyoung Lee ,  Hoi-Jun Yoo
Publisher:   Springer International Publishing AG
Imprint:   Springer International Publishing AG
Edition:   1st ed. 2023
Weight:   0.336kg
ISBN:  

9783031367922


ISBN 10:   3031367928
Pages:   101
Publication Date:   15 August 2023
Audience:   Professional and scholarly ,  Professional & Vocational
Format:   Hardback
Publisher's Status:   Active
Availability:   Manufactured on demand   Availability explained
We will order this item for you from a manufactured on demand supplier.

Table of Contents

Introduction.- Background of Deep Reinforcement Learning.- Group-Sparse Training Algorithm for Accelerating Deep Reinforcement Learning.- An Energy-Efficient Deep Reinforcement Learning Processor Design.- Low-power Autonomous Adaptation System with Deep Reinforcement Learning.- Low-power Autonomous Adaptation System with Deep Reinforcement Learning.- Exponent-Computing-in-Memory for DNN Training Processor with Energy-Efficient Heterogeneous Floating-point Computing Architecture.

Reviews

Author Information

Hoi-Jun Yoo is the KAIST ICT Endowed Chair Professor, School of Electrical Engineering, KAIST. He was the VCSEL pioneer in Bell Communications Research at Red Bank, NJ. USA and Manager of DRAM design group at Hyundai Electronics designing from 1M DRAM to 256M SDRAM. Currently, he is a full professor of Department of Electrical Engineering at KAIST and the director of the System Design Innovation and Application Research Center (SDIA). From 2003 to 2005, he served as the full time Advisor to the Minister of Korean Ministry of Information and Communication for SoC and Next Generation Computing. His current research interests are Bio Inspired IC Design, Network on a Chip, Multimedia SoC design, Wearable Healthcare Systems, and high speed and low power memory. He has published more than 250 papers, and wrote or edited 5 books, “DRAM Design” (1997, Hongneung), “High Performance DRAM”(1999 Hongneung), “Low Power NoC for High Performance SoC Design”(2008, CRC), “Mobile3D Graphics SoC”(2010, Wiley), and “BioMedical CMOS ICs”(Co-editing with Chris Van Hoof, 2010, Springer), and many chapters of books. Dr. Yoo received Order of Service Merit from Korean government in 2011 for his contribution to Korean memory industry, Scientist/Engineer of this month Award from Ministry of Education, Science and Technology of Korea in 2010, Best Scholarship Awards of KAIST in 2011. He also received the Electronic Industrial Association of Korea Award for his contribution to DRAM technology in 1994, Hynix Development Award in 1995, the Korea Semiconductor Industry Association Award in 2002, Best Research of KAIST Award in 2007, and has been co-recipients of ASP-DAC Design Award 2001, Outstanding Design Awards of 2005, 2006, 2007, 2010, 2011, 2014 A-SSCC, Student Design Contest Award of 2007, 2008, 2010, 2011 DAC/ISSCC. He has served as a member of the executive committee of ISSCC, Symposium on VLSI, and A-SSCC. He also served as the IEEE SSCS Distinguished Lecturer ('10-'11) and the TPC chairs of ISSCC 2015, ISWC 2010 and A-SSCC 2008. He is an IEEE Fellow. Juhyoung Lee received a B.S. degree in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea in 2017, and a Ph.D. degree in electrical engineering from the KAIST in 2023. He interned at Silicon Research, Meta Reality Lab, CA, USA, in 2022. He joined Qualcomm, San Diego, CA, USA, in 2023, as a Senior Graphics ASIC Design Engineer. His current research interests include energy-efficient multicore architectures/accelerator ASICs/systems design especially focused on artificial intelligence (AI) including deep neural networks, and graphics applications including ray tracing.

Tab Content 6

Author Website:  

Customer Reviews

Recent Reviews

No review item found!

Add your own review!

Countries Available

All regions
Latest Reading Guide

wl

Shopping Cart
Your cart is empty
Shopping cart
Mailing List