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OverviewIs designed to serve as a comprehensive and up-to-date manual for process, device, layout, and design engineers Covers topics that designers as well as layout and process engineers deal with every day, such as front-end-of-line (FEOL) and back-end-of-line BEOL DRs, coverage DRs, stressors DRs, and modeling, foundry reliability, and advance (20 nm) step-by-step process flow Can be used by those studying semiconductors and microelectronics as well as students and researchers in the fields of electrical engineering, physics, materials engineering, and chemical engineering Full Product DetailsAuthor: Eitan N. Shauly (Tower Semiconductor Ltd, Israel)Publisher: Jenny Stanford Publishing Imprint: Jenny Stanford Publishing ISBN: 9789814968003ISBN 10: 9814968005 Pages: 808 Publication Date: 30 November 2022 Audience: General/trade , General Format: Hardback Publisher's Status: Forthcoming Availability: Not yet available  This item is yet to be released. You can pre-order this item and we will dispatch it to you upon its release. Table of ContentsReviewsAuthor InformationEitan N. Shauly is the director of integration at Tower Semiconductor Ltd., Israel, since 1998. He has been with the organization since 1989, initially as a diffusion and ion implantation engineer and a device/integration engineer and later focusing on process integration, modeling, and design rules as well as incorporating new technology in the company's foundries. Dr Shauly also teaches courses related to VLSI technology in the Faculty of Materials Science and Engineering, Technion - Israel Institute of Technology, Haifa, Israel. He received his BSc (1989) in materials engineering from Ben-Gurion University, Beer-Sheva, Israel, and MSc (1995) and PhD (2001) in materials engineering from the Technion - Israel Institute of Technology. Tab Content 6Author Website:Countries AvailableAll regions |
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