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OverviewCHAPTER 6 Architecting Testbenches 221 Reusable Verification Components 221 Procedural Interface 225 Development Process 226 Verilog Implementation 227 Packaging Bus-Functional Models 228 Utility Packages 231 VHDL Implementation 237 Packaging Bus-Functional Procedures 238 240 Creating a Test Harness 243 Abstracting the Client/Server Protocol Managing Control Signals 246 Multiple Server Instances 247 Utility Packages 249 Autonomous Generation and Monitoring 250 Autonomous Stimulus 250 Random Stimulus 253 Injecting Errors 255 Autonomous Monitoring 255 258 Autonomous Error Detection Input and Output Paths 258 Programmable Testbenches 259 Configuration Files 260 Concurrent Simulations 261 Compile-Time Configuration 262 Verifying Configurable Designs 263 Configurable Testbenches 265 Top Level Generics and Parameters 266 Summary 268 CHAPTER 7 Simulation Management 269 Behavioral Models 269 Behavioral versus Synthesizable Models 270 Example of Behavioral Modeling 271 Characteristics of a Behavioral Model 273 x Writing Testbenches: Functional Verification of HDL Models Modeling Reset 276 Writing Good Behavioral Models 281 Behavioral Models Are Faster 285 The Cost of Behavioral Models 286 The Benefits of Behavioral Models 286 Demonstrating Equivalence 289 Pass or Fail? 289 Managing Simulations 292 294 Configuration Management Verilog Configuration Management 295 VHDL Configuration Management 301 SDF Back-Annotation 305 Output File Management 309 Regression 312 Running Regressions 313 Regression Management 314 Summary 316 APPENDIX A Coding Guidelines 317 Directory Structure 318 VHDL Specific 320 Verilog Specific 320 General Coding Guidelines 321 Comments 321 Layout 323 Syntax 326 Debugging 329 Naming Guidelines 329 Capitalization 330 Identifiers 332 Constants 334 334 HDL SpecificFilenames 336 HDL Coding Guidelines 336 337 Structure 337 Layout Full Product DetailsAuthor: Janick BergeronPublisher: Springer-Verlag New York Inc. Imprint: Springer-Verlag New York Inc. Edition: Softcover reprint of the original 1st ed. 2002 Dimensions: Width: 15.50cm , Height: 2.00cm , Length: 23.50cm Weight: 0.581kg ISBN: 9781475783445ISBN 10: 1475783442 Pages: 354 Publication Date: 14 April 2013 Audience: Professional and scholarly , Professional & Vocational Format: Paperback Publisher's Status: Active Availability: Manufactured on demand  We will order this item for you from a manufactured on demand supplier. Table of ContentsWhat is Verification?.- Verification Tools.- The Verification Plan.- Behavioral Hardware Description Languages.- Stimulus and Response.- Architecting Testbenches.- Simulation Management.ReviewsThe bible for techniques in writing effective, readable and reusable Verilog and VHDL testbenches within a best-in-class verification process. Ben Cohen - VHDLCohen Training The bible for techniques in writing effective, readable and reusable Verilog and VHDL testbenches within a best-in-class verification process. Ben Cohen - VHDLCohen Training Author InformationTab Content 6Author Website:Countries AvailableAll regions |
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