Overview
This text presents the theory of wave pipelined operation of digital circuits and discusses practical design techniques for the realization of wave pipelined circuits in CMOS technology. Wave pipelining is a timing methodology used in digital systems to enhance performance while conserving the number of data registers used. This is achieved by applying new data to the inputs of a combinatorial logic block before the previous outputs are available. In contrast to conventional pipelining, system performance is limited by differences in maximum and minimum circuit delay rather than maximum circuit delays. Realization of practical systems using this technique requires accurate system level and circuit level timing analysis. At the system level, timing constraints identifying valid regions of operation for correct clocking of wave pipelined circuits are presented. Both single stage and multiple stage systems including feedback are considered. At the circuit level, since performance is determined by the maximum circuit delay difference, highly accurate estimates of both maximum and minimum delays are needed. Thus, timing analysis based on traditional gate delay models is not sufficient. For CMOS circuits, data dependent delay models considering the effect of simultaneous multiple input switchings must be used. An algorithm using these delay models for accurate analysis of small to medium sized circuits is implemented in a prototype timing analyzer, XTV. Results are given for a set of benchmark circuits.
Full Product Details
Author: C. Thomas Gray ,
Wentai Liu ,
Ralph K. Cavin, III
Publisher: Springer
Imprint: Springer
Edition: 1994 ed.
Volume: 248
Dimensions:
Width: 15.50cm
, Height: 1.40cm
, Length: 23.50cm
Weight: 1.100kg
ISBN: 9780792393986
ISBN 10: 0792393988
Pages: 206
Publication Date: 30 November 1993
Audience:
General/trade
,
Professional and scholarly
,
Professional & Vocational
Format: Hardback
Publisher's Status: Active
Availability: In Print

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