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OverviewThis text presents the theory of wave pipelined operation of digital circuits and discusses practical design techniques for the realization of wave pipelined circuits in CMOS technology. Wave pipelining is a timing methodology used in digital systems to enhance performance while conserving the number of data registers used. This is achieved by applying new data to the inputs of a combinatorial logic block before the previous outputs are available. In contrast to conventional pipelining, system performance is limited by differences in maximum and minimum circuit delay rather than maximum circuit delays. Realization of practical systems using this technique requires accurate system level and circuit level timing analysis. At the system level, timing constraints identifying valid regions of operation for correct clocking of wave pipelined circuits are presented. Both single stage and multiple stage systems including feedback are considered. At the circuit level, since performance is determined by the maximum circuit delay difference, highly accurate estimates of both maximum and minimum delays are needed. Thus, timing analysis based on traditional gate delay models is not sufficient. For CMOS circuits, data dependent delay models considering the effect of simultaneous multiple input switchings must be used. An algorithm using these delay models for accurate analysis of small to medium sized circuits is implemented in a prototype timing analyzer, XTV. Results are given for a set of benchmark circuits. Full Product DetailsAuthor: C. Thomas Gray , Wentai Liu , Ralph K. Cavin, IIIPublisher: Springer Imprint: Springer Edition: 1994 ed. Volume: 248 Dimensions: Width: 15.50cm , Height: 1.40cm , Length: 23.50cm Weight: 1.100kg ISBN: 9780792393986ISBN 10: 0792393988 Pages: 206 Publication Date: 30 November 1993 Audience: General/trade , Professional and scholarly , Professional & Vocational Format: Hardback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of Contents1 Introduction and Motivation.- 1.1 Wave Pipelining.- 1.2 History.- 1.3 Designing Wave Pipelined Circuits.- 1.4 Organization.- 2 Clock Period Constraints: Single Stage Systems.- 2.1 Introduction.- 2.2 System Model.- 2.3 Constraints for Correct Clocking.- 2.4 Minimizing the Clock Period.- 2.5 The Parameter k.- 2.6 Special Cases.- 2.7 Conclusions.- 3 Clock Period Constraints: Multiple Stage Systems.- 3.1 Introduction.- 3.2 System Model.- 3.3 Constraints for Correct Clocking.- 3.4 Example.- 3.5 Conclusions.- 4 Exact Timing Analysis.- 4.1 Introduction.- 4.2 Motivation and Justification.- 4.3 Complexity of Problem.- 4.4 Notation and Model.- 4.5 Basic Algorithm Development.- 4.6 Conclusion.- 5 Exact Timing Analysis: Algorithm.- 5.1 Introduction.- 5.2 Algorithm Strategy.- 5.3 Calculation of Output Responses.- 5.4 Verification of Output Responses.- 5.5 Detection of Components.- 5.6 Vector Reporting.- 5.7 Implementation.- 5.8 Limitations and Extensions.- 5.9 Conclusion.- 6 Practical Considerations in Wave Pipelining.- 6.1 Architecture Choice.- 6.2 Path Delay Variation.- 6.3 Circuit Choice.- 6.4 Parametric Variations due to Manufacturing and Environmen-tal Factors.- 6.5 Clock Distribution and Physical Layout.- 6.6 Technology Scaling.- 6.7 Conclusion.- 7 Design Examples.- 7.1 Introduction.- 7.2 Parallel-Carry Adder.- 7.3 Sampler.- 7.4 Conclusion.- 8 Conclusions.- A Example Model File.- B Calculation of Tolerance of Parametric Variations.- References.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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