VLSI-SoC: From Systems to Silicon: IFIP TC10/ WG 10.5 Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2005), October 17-19, 2005, Perth, Australia

Author:   Ricardo Reis ,  Adam Osseiran ,  Hans-Joerg Pfleiderer
Publisher:   Springer-Verlag New York Inc.
Edition:   2007 ed.
Volume:   240
ISBN:  

9780387736600


Pages:   344
Publication Date:   22 August 2007
Format:   Hardback
Availability:   Awaiting stock   Availability explained
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VLSI-SoC: From Systems to Silicon: IFIP TC10/ WG 10.5 Thirteenth International Conference on Very Large Scale Integration of System on Chip (VLSI-SoC2005), October 17-19, 2005, Perth, Australia


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Overview

This book contains extended and revised versions of the best papers that were presented during the thirteenth edition of the IFIP TC10/WG10.5 International Conference on Very Large Scale Integration, a Global System-on-a-Chip Design & CAD conference. The 13th conference was held at the Parmelia Hilton Hotel, Perth, Western Australia (October 17-19, 2005). Previous conferences have taken place in Edinburgh, Trondheim, Vancouver, Munich, Grenoble, Tokyo, Gramado, Lisbon, Montpellier and Darmstadt. The purpose of this conference, sponsored by IFIP TC 10 Working Group 10.5, is to provide a forum to exchange ideas and show industrial and academic research results in the field of mic- electronics design. The current trend toward increasing chip integ- tion and technology process advancements brings about stimulating new challenges both at the physical and system-design levels, as well in the test of these systems. VLSI-SOC conferences aim to address these exciting new issues. The 2005 edition of VLSI-SoC maintained the traditional structure, which has been successful at the previous VLSI-SOC conferences. The quality of submissions (107 papers from 26 countries) made the selection process difficult, but finally 63 papers and 25 posters were accepted for presentation in VLSI-SoC 2005. Out of the 63 full papers presented at the conference, 20 were chosen by a selection committee to have an extended and revised version included in this book. These selected papers came from Australia, Brazil, France, Germany, Italy, Korea, Portugal, Sweden, Switzerland, United Kingdom and the United States of America. x Preface

Full Product Details

Author:   Ricardo Reis ,  Adam Osseiran ,  Hans-Joerg Pfleiderer
Publisher:   Springer-Verlag New York Inc.
Imprint:   Springer-Verlag New York Inc.
Edition:   2007 ed.
Volume:   240
Dimensions:   Width: 15.50cm , Height: 2.00cm , Length: 23.50cm
Weight:   0.691kg
ISBN:  

9780387736600


ISBN 10:   0387736603
Pages:   344
Publication Date:   22 August 2007
Audience:   College/higher education ,  Professional and scholarly ,  Postgraduate, Research & Scholarly ,  Professional & Vocational
Format:   Hardback
Publisher's Status:   Active
Availability:   Awaiting stock   Availability explained
The supplier is currently out of stock of this item. It will be ordered for you and placed on backorder. Once it does come back in stock, we will ship it out for you.

Table of Contents

Molecular Electronics – Devices and Circuits Technology.- Improving DPA Resistance of Quasi Delay Insensitive Circuits Using Randomly Time-shifted Acknowledgment Signals.- A Comparison of Layout Implementations of Pipelined and Non-Pipelined Signed Radix-4 Array Multiplier and Modified Booth Multiplier Architectures.- Defragmentation Algorithms for Partially Reconfigurable Hardware.- Technology Mapping for Area Optimized Quasi Delay Insensitive Circuits.- 3D-SoftChip: A Novel 3D Vertically Integrated Adaptive Computing System.- Caronte: A methodology for the Implementation of Partially dynamically Self-Reconfiguring Systems on FPGA Platforms.- A Methodology for Reliability Enhancement of Nanometer-Scale Digital Systems Based on a-priori Functional Fault- Tolerance Analysis.- Issues in Model Reduction of Power Grids.- A Traffic Injection Methodology with Support for System-Level Synchronization.- Pareto Points in SRAM Design Using the Sleepy Stack Approach.- Modeling the Traffic Effect for the Application Cores Mapping Problem onto NoCs.- Modular Asynchronous Network-on-Chip: Application to GALS Systems Rapid Prototyping.- A Novel MicroPhotonic Structure for Optical Header Recognition.- Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint.- On-chip Pseudorandom Testing for Linear and Nonlinear MEMS.- Scan Cell Reordering for Peak Power Reduction during Scan Test Cycles.- On The Design of A Dynamically Reconfigurable Function-Unit for Error Detection and Correction.- Exact BDD Minimization for Path-Related Objective Functions.- Current Mask Generation: an Analog Circuit to Thwart DPA Attacks.- A Transistor Placement Technique Using Genetic Algorithm and Analytical Programming.

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