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OverviewThis book presents extended and revised versions of the best papers that were presented during the twelfth edition of the IFIP TC10 Working Group 10.5 International Conference on Very Large Scale Integration. The purpose of this conference was to provide a forum to exchange ideas and show research results in the field of microelectronics design. The current trend toward increasing chip integration brings about exhilarating new challenges both at the physical and system-design levels. This book aims to address these exciting issues. Full Product DetailsAuthor: Manfred Glesner , Ricardo Reis , Leandro Indrusiak , Vincent MooneyPublisher: Springer-Verlag New York Inc. Imprint: Springer-Verlag New York Inc. Edition: Softcover reprint of hardcover 1st ed. 2006 Volume: 200 Dimensions: Width: 15.50cm , Height: 1.70cm , Length: 23.50cm Weight: 0.504kg ISBN: 9781441941268ISBN 10: 1441941266 Pages: 314 Publication Date: 19 November 2010 Audience: Professional and scholarly , Professional & Vocational Format: Paperback Publisher's Status: Active Availability: Out of print, replaced by POD  We will order this item for you from a manufatured on demand supplier. Table of ContentsEffect of Power Optimizations on Soft Error Rate.- Dynamic Models for Substrate Coupling in Mixed-Mode Systems.- Hinoc: A Hierarchical Generic Approach for on-Chip Communication, Testing and Debugging of SoCs.- Automated Conversion of SystemC Fixed-Point Data Types.- Exploration of Sequential Depth by Evolutionary Algorithms.- Validation of Asynchronous Circuit Specifications Using IF/CADP.- On-Chip Property Verification Using Assertion Processors.- Run-Time FPGA Reconfiguration for Power-/Cost-Optimized Real-time Systems.- A Switched Opamp Based 10 Bits Integrated ADC for Ultra Low Power Applications.- Exploring the Capabilities of Reconfigurable Hardware for OFDM-Based Wlans.- Software-Based Test for Nonprogrammable Cores in Bus-Based System-On-Chip Architectures.- Optimizing SOC Test Resources Using Dual Sequences.- A Novel full Automatic Layout Generation Strategy for Static CMOS Circuits.- Low Power Java Processor for Embedded Applications.- Impact of Gate Leakage on Efficiency of Circuit Block Switch-Off Schemes.- Evaluation Methodology for Single Electron Encoded Threshold Logic Gates.- Asynchronous Integration of Coarse-Grained Reconfigurable XPP-Arrays Into Pipelined Risc Processor Datapath.- Gray Encoded Arithmetic Operators Applied to FFT and FIR Dedicated Datapaths.- Stuck-At-Fault Testability of SPP Three-Level Logic Forms.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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