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OverviewVLSI systems are becoming very complex and difficult to test. Traditional stuck-at fault problems may be inadequate to model possible manufacturing defects in the integrated ciruit. Hierarchial models are needed that are easy to use at the transistor and functional levels. Stuck-open faults present severe testing problems in CMOS circuits, to overcome testing problems testable designs are utilized. Bridging faults are important due to the shrinking geometry of ICs. BIST PLA schemes have common features-controllability and observability - which are enhanced through additional logic and test points. Certain circuit topologies are more easily testable than others. The amount of reconvergent fan-out is a critical factor in determining realistic measures for determining test generation difficulty. Test implementation is usually left until after the VLSI data path has been synthesized into a structural description. This leads to investigation methodologies for performing design synthesis with test incorporation. These topics and more are discussed. Full Product DetailsAuthor: George W. ZobristPublisher: Bloomsbury Publishing Plc Imprint: Praeger Publishers Inc Dimensions: Width: 16.00cm , Height: 1.70cm , Length: 23.00cm Weight: 0.450kg ISBN: 9780893917814ISBN 10: 0893917818 Pages: 200 Publication Date: 01 May 1993 Audience: College/higher education , Professional and scholarly , Undergraduate , Postgraduate, Research & Scholarly Format: Hardback Publisher's Status: Active Availability: Manufactured on demand  We will order this item for you from a manufactured on demand supplier. Table of ContentsPhysical fault modelling and simulation for VLSI MOS circuits; designing CMOS gates to test open faults; testing bridging faults assignment implication constraints an design for testability; testable design synthesis models.ReviewsAuthor Informationbrist /f George /i W. Tab Content 6Author Website:Countries AvailableAll regions |
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