Free Delivery Over $100
|
|
|||
|
||||
OverviewError-correcting codes are ubiquitous. They are adopted in almost every modern digital communication and storage system, such as wireless communications, optical communications, Flash memories, computer hard drives, sensor networks, and deep-space probing. New-generation and emerging applications demand codes with better error-correcting capability. On the other hand, the design and implementation of those high-gain error-correcting codes pose many challenges. They usually involve complex mathematical computations, and mapping them directly to hardware often leads to very high complexity. VLSI Architectures for Modern Error-Correcting Codes serves as a bridge connecting advancements in coding theory to practical hardware implementations. Instead of focusing on circuit-level design techniques, the book highlights integrated algorithmic and architectural transformations that lead to great improvements on throughput, silicon area requirement, and/or power consumption in the hardware implementation. The goal of this book is to provide a comprehensive and systematic review of available techniques and architectures, so that they can be easily followed by system and hardware designers to develop en/decoder implementations that meet error-correcting performance and cost requirements. This book can be also used as a reference for graduate-level courses on VLSI design and error-correcting coding. Particular emphases are placed on hard- and soft-decision Reed-Solomon (RS) and Bose-Chaudhuri-Hocquenghem (BCH) codes, and binary and non-binary low-density parity-check (LDPC) codes. These codes are among the best candidates for modern and emerging applications due to their good error-correcting performance and lower implementation complexity compared to other codes. To help explain the computations and en/decoder architectures, many examples and case studies are included. More importantly, discussions are provided on the advantages and drawbacks of different implementation approaches and architectures. Full Product DetailsAuthor: Xinmiao Zhang (Case Western Reserve University, Cleveland, Ohio, USA and SanDisk, Milpitas, California, USA)Publisher: Taylor & Francis Inc Imprint: CRC Press Inc Dimensions: Width: 15.60cm , Height: 2.80cm , Length: 23.40cm Weight: 0.725kg ISBN: 9781482229646ISBN 10: 1482229641 Pages: 410 Publication Date: 24 July 2015 Audience: General/trade , College/higher education , General , Tertiary & Higher Education Format: Hardback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of ContentsFinite Field Arithmetic. VLSI Architecture Design Fundamentals. Root Computations for Polynomials Over Finite Fields. Reed-Solomon Encoder and Hard-Decision Decoder Architectures. Algebraic Soft-Decision Reed-Solomon Decoder Architectures. Interpolation-Based Chase and Generalized Minimum Distance Decoders. BCH Encoder and Decoder Architectures. Binary LDPC Codes and Decoder Architectures. Non-Binary LDPC Decoder Architectures.ReviewsError-correction coding has become an ineluctable feature for the development of modern telecommunication and storage systems. The VLSI implementation of powerful error-correcting codes and decoders with a minimum hardware resource is especially of great importance for the integration of the codes in high-speed, low consumption circuits. Such implementation requires a deep understanding of both mathematical theory of the codes and VLSI architecture design of their decoders, a dual expertise that Dr. Xinmiao Li was able to transcribe with high rigor and clarity in this book. From cyclic codes to the more recent binary and non-binary LDPC codes, this book equip any engineer or researcher with the necessary knowledge to implement the state-of-the-art and up-to-date solutions. -Prof. David Declercq, Director General of Research at the ENSEA, Cergy-Pontoise, France This book is unique in its synthesis of the advanced concepts in abstract algebra, decoding algorithms and architecture used masterfully to introduce VLSI implementations of highly sophisticated decoders of modern error correction codes. -Bane Vasic, University of Arizona Error-correction coding has become an ineluctable feature for the development of modern telecommunication and storage systems. The VLSI implementation of powerful error-correcting codes and decoders with a minimum hardware resource is especially of great importance for the integration of the codes in high-speed, low consumption circuits. Such implementation requires a deep understanding of both mathematical theory of the codes and VLSI architecture design of their decoders, a dual expertise that Dr. Xinmiao Zhang was able to transcribe with high rigor and clarity in this book. From cyclic codes to the more recent binary and non-binary LDPC codes, this book equips any engineer or researcher with the necessary knowledge to implement state-of-the-art solutions. -Prof. David Declercq, Director General of Research at the ENSEA, Cergy-Pontoise, France This book is unique in its synthesis of the advanced concepts in abstract algebra, decoding algorithms and architecture used masterfully to introduce VLSI implementations of highly sophisticated decoders of modern error correction codes. -Bane Vasic, University of Arizona Author InformationXinmiao Zhang received her Ph.D in electrical engineering from the University of Minnesota, Twin Cities, USA. She is currently an Associate Professor in the Department of Electrical and Computer Engineering at The Ohio State University. Previously, she was a Timothy E. and Allison L. Schroeder Associate Professor at Case Western Reserve University, Cleveland, Ohio. Between her academic positions, she continued her research on error-correcting codes at SanDisk/Western Digital Corporation. She has also been a visiting professor at Qualcomm and spent her sabbatical leave at the University of Washington, Seattle, USA. Her research focuses on VLSI architecture design for communications, digital signal processing, and cryptography. She is a recipient of the National Science Foundation Faculty Early Career Development (CAREER) Award. Tab Content 6Author Website:Countries AvailableAll regions |
||||
