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OverviewVHDL is a comprehensive language that allows a user to deal with design complexity. Design, and the data representing a design, are complex by the very nature of a modern digital system constructed from VLSI chips. VHDL is the first language to allow one to capture all the nuances of that complexity, and to effectively manage the data and the design process. As this book shows, VHDL is not by its nature a complex language. In 1980, the U. S. Government launched a very aggressive effort to advance the state-of-the-art in silicon technology. The objective was to significantly enhance operating performance and circuit density for Very Large Scale Integration (VLSI) silicon chips. The U. S. Government realized that in order for contractors to be able to work together to develop VLSI products, to document the resulting designs, to be able to reuse the designs in future products, and to efficiently upgrade existing designs, they needed a common communication medium for the design data. They wanted the design descriptions to be computer readable and executable. They also recognized that with the high densities envisioned for the U. S. Government's Very High Speed Integrated Circuit (VHSIC) chips and the large systems required in future procurements, a means of streamlining the design process and managing the large volumes of design data was required. Thus was born the concept of a standard hardware design and description language to solve all of these problems. Full Product DetailsAuthor: Roger Lipsett , Carl F. Schaefer , Cary UsseryPublisher: Springer Imprint: Springer Edition: 1989 ed. Dimensions: Width: 15.60cm , Height: 1.90cm , Length: 23.40cm Weight: 1.390kg ISBN: 9780792390305ISBN 10: 079239030 Pages: 299 Publication Date: 30 June 1989 Audience: College/higher education , Professional and scholarly , Postgraduate, Research & Scholarly , Professional & Vocational Format: Hardback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of Contents1 — Introduction.- Why VHDL.- Terminology and Conventions.- 2 — A Model of Hardware.- A Model of Behavior.- A Model of Time.- A Model of Structure.- 3 — Basics.- Structure and Behavior.- Data Types and Objects.- Hooking Constructs Together.- Major VHDL Constructs.- Libraries.- 4 — Data Types.- Literals.- Scalar Types.- Composite Types.- Subtypes.- Attributes.- Predefined Operators.- 5 — Behavioral Description.- Process Statements.- Behavioral Modeling — Sequential View.- Behavioral Modeling — Concurrent View.- 6 — Structural Description.- Basic Features of Structural Description.- Regular Structures.- Configuration Specifications.- Default Values and Unconnected Ports.- 7 — Large Scale Design.- Managing Shared Designs.- Visibility and the Analysis Context.- Partitioning a Design.- Sharing Data Within a Design.- Specifying a Design Configuration.- Mixing Structure and Behavior.- 8 — A Complete Example.- The Traffic Light Controller.- Creating the Specification.- Partitioning the Design.- Starting the Implementation.- Setting Up the PLA.- 9 — Advanced Features.- Overloading.- Access Types.- File Types and I/O.- User-Defined Attributes.- Signal-Related Attributes.- Aliases.- Association by Subelement.- Guarded Assignment Statements.- Disconnection Specifications.- Null Transactions.- 10 — VHDL in Use.- A Device Controller.- Setup and Hold Timing.- A Neural Net.- A Systolic Array Multiplier.- Summary.- Appendix A — Predefined Environment261.- Reserved Words.- Attributes.- Type and Subtype Attributes.- Array Attributes.- Signal-Valued Attributes.- Signal-Related Attributes.- Packages.- The Package STANDARD.- The Package TEXTIO.- >Appendix B — VHDL Syntax.- >Appendix C — Suggested Reading.- >Index.Reviews... this is a most useful publication.' Journal of Semicustom ICs 8 (3) 1991 `... this is a most useful publication.' Journal of Semicustom ICs 8 (3) 1991 Author InformationTab Content 6Author Website:Countries AvailableAll regions |
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