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OverviewThe emergence of VHDL, as a standard for hardware description languages helped disseminate the use of such languages among IC designers. The creation of the standard however does not mean that all work has ceased. Research continues in the use of the language and on improvements of the standard. This book presents recent research on four key issues related to the use of VHDL. The first part covers simulation of circuits using VHDL in which timing and switching are central themes. Part 2 looks at the combination of synthesis and VHDL in designing circuits. This includes a case study of chip design using silicon 1076. Advances in the formal verification of VHDL designs are given in Part 3. This relatively new area in the use of VHDL is developing rapidly into an important issue for speeding the design of circuits. The final part considers modelling issues and system level design. The contributions to this volume are based on specially selected papers from EURO-VHDL conferences in 1990 and 1991. These papers have been updated and expanded to give the reader a current state of the art in the use of VHDL in circuit design. Full Product DetailsAuthor: Jean MermetPublisher: Springer Imprint: Springer Edition: 1992 ed. Volume: 183 Dimensions: Width: 15.50cm , Height: 1.90cm , Length: 23.50cm Weight: 1.380kg ISBN: 9780792392538ISBN 10: 0792392531 Pages: 307 Publication Date: 31 May 1992 Audience: College/higher education , Professional and scholarly , Postgraduate, Research & Scholarly , Professional & Vocational Format: Hardback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of ContentsEvolutionary Processes in Language, Software, and System Design.- Timing Constraint Checks in VHDL—a comparative study.- Using Formalized Timing Diagrams in VHDL Simulation.- Switch-Level Models in Multi-Level VHDL Simulations.- Bi-Directional Switches in VHDL using the 46 Value System.- Systems Real Time Analysis with VHDL Generated from Graphical SA-VHDL.- Delay Calculation and Back Annotation in VHDL Addressing the Requirements of ASIC Design.- A VHDL-Driven Synthesis Environment.- VHDL Specific Issues in High Level Synthesis.- ASIC Design Using Silicon 1076.- Generating VHDL for Simulation and Synthesis from a High-Level DSP Design Tool.- Aspects of Optimization and Accuracy for VHDL Synthesis.- Symbolic Computation of Hierarchical and Interconnected FSMS.- Formal Semantics of VHDL Timing Constructs.- Structural Information Model of VHDL.- Formal Verification of VHDL Descriptions in Boyer-Moore: First Results.- Developing a Formal Semantic Definition of VHDL.- Approaching System Level Design.- Incremental Design—Application of a Software-Based Method for High-Level Hardware Design with VHDL.- Introducing CASCADE control graphs in VHDL.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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