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OverviewVHDL is the most widespread standard for hardware description. From its initial applications in simulation and ASIC description, VHDL is now being used in a wide range of applications at all levels, from system down to gate. The applications, which include synthesis and formal proof, make VHDL a design support tool as well as a deliverable. The use of VHDL implies a new approach to design. The VHDL Designer's Reference offers engineers and students practical help in addressing real problems encountered when implementing and using VHDL in their companies or research laboratories. It is thus a valuable reference for all practising designers. Intended for the experienced designer, VHDL Designer's Reference discusses modeling issues, design methods, efficiency tricks and portability traps. It also compares VHDL with other hardware description languages such as M, Verilog, and UDL/I. This complete reference provides a resource to help improve the designer's use of VHDL. Full Product DetailsAuthor: Jean-Michel Bergé , Alain Fonkoua , Serge Maginot , Jacques RouillardPublisher: Springer Imprint: Springer Edition: 1992 ed. Dimensions: Width: 15.50cm , Height: 2.60cm , Length: 23.50cm Weight: 1.870kg ISBN: 9780792317562ISBN 10: 0792317564 Pages: 455 Publication Date: 31 May 1992 Audience: College/higher education , Professional and scholarly , Postgraduate, Research & Scholarly , Professional & Vocational Format: Hardback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of Contents1. Introduction.- 1.1. VHDL Status.- 1.2. The VHDL Spectrum.- 1.3. Models, Modeling, and Modelware.- 1.4. The Other Languages and Formats.- 2. VHDL Tools.- 2.1. Introduction.- 2.2. Evaluating VHDL tools.- 2.3. Technology of Platforms.- 3. VHDL and Modeling Issues.- 3.1. Introduction.- 3.2. Core VHDL Concepts.- 3.3. Abstraction.- 3.4. Hierarchy.- 3.5. Modularity.- 3.6. Reusability.- 3.7. Portability.- 3.8. Efficiency.- 3.9. Documentation.- 3.10. Synthesis.- 3.11. Conclusion.- 4. Structuring the Environment.- 4.1. Choosing a Logic System.- 4.2. Utility Packages.- 5. System Modeling.- 5.1. Introduction.- 5.2. The FSM with a Single Thread of Control.- 5.3. Multiple Threads of Control.- 5.4. Hierarchy: State Charts and S-Nets.- 5.5. Conclusion.- 6. Structuring Methodology.- 6.1. Structuring.- 6.2. What are the Possibilities of VHDL?.- 6.3. To Summarize.- 7. Tricks and Traps.- 7.1. Modeling Traps.- 7.2. Modeling Tricks.- 7.3. Pitfalls.- 7.4. Designer.- 8. M and VHDL.- 8.1. Introduction.- 8.2. Design Unit.- 8.3. Sequential and Concurrent Domains.- 8.4. Objects.- 8.5. Predefined Operators.- 8.6. Statements.- 8.7. Description Level.- 8.8. Translating from M to VHDL.- 8.9. Conclusion.- 9. Verilog and VHDL.- 9.1. Introduction.- 9.2. Design Unit.- 9.3. Sequential and Concurrent Domains.- 9.4. Objects.- 9.5. Predefined Operators.- 9.6. Statements.- 9.7. Description Level.- 9.8. Translating from Verilog to VHDL.- 9.9. Conclusion.- 10. UDL/I and VHDL.- 10.1. Introduction.- 10.2. Design Unit.- 10.3. Sequential and Concurrent Domains.- 10.4. Objects.- 10.5. UDL/I Structural Description.- 10.6. UDL/I Behavioral Description.- 10.7. UDL/I Assertion Section.- 10.8. Description Level.- 10.9. Translating from UDL/I to VHDL.- 10.10. Conclusion.- 11. Memo.- 12. Index.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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