Free Delivery Over $100
|
|
|||
|
||||
OverviewThis book addresses ""front end"" questions and issues encountered in using the Verilog HDL, during all the stages of Hardware Design, Synthesis and Verification. The issues discussed in the book are typically encountered in both ASIC design projects as well as in Soft IP designs. These issues are addressed in a simple Q&A format. Since each issue is independently dealt with and explained in detail, this book acts as an important source of reference for the Verilog users. Each of the FAQs will be illustrated with figures and tables as required. The latest Verilog-2001 and SystemVerilog have also been referred to in this book. With the increasing complexity of ASICs being designed these days, the decisions that one makes in any of the stages of Design, Synthesis or Verification has profound effects on these three stages. This book presents the intricacies of these inter-dependent issues in the context of the Verilog HDL. Full Product DetailsAuthor: Shivakumar S. Chonnad , Needamangalam B. BalachanderPublisher: Springer-Verlag New York Inc. Imprint: Springer-Verlag New York Inc. Edition: Softcover reprint of the original 1st ed. 2004 Dimensions: Width: 15.50cm , Height: 1.40cm , Length: 23.50cm Weight: 0.840kg ISBN: 9781441919861ISBN 10: 1441919864 Pages: 238 Publication Date: 01 December 2010 Audience: Professional and scholarly , Professional & Vocational Format: Paperback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of ContentsReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
||||
