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Full Product Details

Author:   Bob Zeidman
Publisher:   Pearson Education (US)
Imprint:   Prentice Hall
Dimensions:   Width: 24.20cm , Height: 3.00cm , Length: 18.00cm
Weight:   0.649kg
ISBN:  

9780130811547

ISBN 10:   0130811548
Pages:   432
Publication Date:   22 July 1999
Audience:   College/higher education ,  Tertiary & Higher Education
Format:   Paperback
Publisher's Status:   Out of Print
Availability:   Out of stock  

Table of Contents

I. CODING TECHNIQUES. 1. General Coding Techniques. Code Structure. Comments. Do Not Use Disable Instructions. 2. Behavioral Coding Techniques. Eliminate Periodic Instructions. Eliminate Event Order Dependencies. 3. RTL Coding Techniques. Synchronous Design. Allowable Uses of Asynchronous Logic. 4. Synthesis Issues. Correlated Unknown Signals. State Machines. Optimizing Out Terms. Always Blocks. 5. Simulation Issues. Simulate The Corner Cases. Use Code Coverage Tools. Use The Triple Equals. Use The $display And $stop Statements. II. BASIC BUILDING BLOCKS. 6. The J-K Flip Flop. Behavioral Code. RTL Code. Simulation Code. 7. The Shift Register. Behavioral Code. RTL Code. Simulation Code. 8. The Counter. Behavioral Code. RTL Code. Simulation Code. 9. The Adder. Behavioral Code. RTL Code. Simulation Code. III. STATE MACHINES. 10. The Moore State Machine. Behavioral Code. RTL Code. Simulation Code. 11. The Mealy State Machine. Behavioral Code. RTL Code. Simulation Code. 12. The One-Hot State Machine for FPGAs. RTL Code. Simulation Code. IV. MISCELLANEOUS COMPLEX FUNCTIONS. 13. The Linear Feedback Shift Register (LFSR). Behavioral Code. RTL Code. Simulation Code. 14. The Encrypter/Decrypter. Behavioral Code. RTL Code. Simulation Code. 15. The Phase Locked Loop (PLL). Behavioral Code. RTL Code. Simulation Code. 16. The Unsigned Integer Multiplier. Behavioral Code. RTL Code. Simulation Code. 17. The Signed Integer Multiplier. Behavioral Code. RTL Code. Simulation Code. V. ERROR DETECTION AND CORRECTION. 18. The Parity Generator and Checker. Implementation Code. Simulation Code. 19. Hamming Code Logic. Implementation Code. Simulation Code. 20. The Checksum. Implementation Code. Simulation Code. 21. The Cyclic Redundancy Check (CRC). Behavioral Code. RTL Code. Simulation Code. VI. MEMORIES. 22. The Random Access Memory (RAM). Implementation Code. Simulation Code. 23. The Dual Port RAM. Implementation Code. Simulation Code. 24. The Synchronous FIFO. Behavioral Code. RTL Code. Simulation Code. 25. The Synchronizing FIFO. Behavioral Code. RTL Code. Simulation Code. VII. MEMORY CONTROLLERS. 26. The SRAM/ROM Controller. Behavioral Code. RTL Code. Simulation Code. 27. The Synchronous SRAM Controller. Behavioral Code. RTL Code. Simulation Code. 28. The DRAM Controller. Behavioral Code. RTL Code. Simulation Code. 29. The Fast Page Mode DRAM Controller. Behavioral Code. RTL Code. Simulation Code. Appendix A: Resources. Glossary. Index.

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Author Information

Bob Zeidman is the founder, president and CEO of The Chalkboard Network (www.chalknet.com), a company that provides training for high-tech professionals via the Internet. Previously, Bob was the president of Zeidman Consulting where he designed ASICs, FPGAs, and PC boards for various real-time systems. His clients included Apple Computer, Cisco Systems, Ricoh Systems, and Texas Instruments. He has written technical papers on hardware and software design methods, and has taught courses on Verilog, ASIC design, and FPGA design at conferences throughout the world. He holds a Master's degree from Stanford University and two Bachelor's degrees from Cornell University.

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