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OverviewThis book will explain how to verify SoC logic designs using formal and semi-formal verification techniques. The critical issue to be addressed is whether the functionality of the design is the one that the designers intended. Simulation has been used for checking the correctness of SoC designs (as in functional verification), but many subtle design errors cannot be caught by simulation. Recently, formal verification, giving mathematical proof of the correctness of designs, has been getting much more attention. So far, most of the books on formal verification target the register transfer level (RTL) or lower levels of design. For higher design productivity, it is essential to debug designs as early as possible. That is, designs should be completely verified at very abstracted design levels (higher than RTL). This book covers all aspects of high-level formal and semi-formal verification techniques for system level designs. Full Product DetailsAuthor: Masahiro Fujita , Indradeep Ghosh , Mukul PrasadPublisher: Elsevier Science & Technology Imprint: Elsevier Science & Technology ISBN: 9786611049645ISBN 10: 6611049649 Pages: 256 Publication Date: 01 January 2008 Audience: General/trade , General Format: Electronic book text Publisher's Status: Active Availability: Out of stock  The supplier is temporarily out of stock of this item. It will be ordered for you on backorder and shipped when it becomes available. Table of ContentsReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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