Overview

The book all semiconductor device engineers must read to gain a practical feel for latchup-induced failure to produce lower-cost and higher-density chips. Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process. Presents real cases and solutions that occur in commercial CMOS IC chips Equips engineers with the skills to conserve chip layout area and decrease time-to-market Written by experts with real-world experience in circuit design and failure analysis Distilled from numerous courses taught by the authors in IC design houses worldwide The only book to introduce TLU under system-level ESD and EFT tests This book is essential for practicing engineers involved in IC design, IC design management, system and application design, reliability, and failure analysis. Undergraduate and postgraduate students, specializing in CMOS circuit design and layout, will find this book to be a valuable introduction to real-world industry problems and a key reference during the course of their careers.

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9780470824078

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Ming-Dou Ker is a Professor of Electronics Engineering at National Chiao-Tung University, where he also serves as the Director of the College of Electrical Engineering and Computer Science Master's Degree Program. He is also the Associate Executive Director of Taiwan's National Science and Technology Program on System-on-Chip, and in the past has worked as the Department Manager in the VLSI Design Division of the Computer and Communication Research Laboratories (CCL), Industrial Technology Research Institute (ITRI). Ker has published 300 technical papers in international journals and conferences related to reliability and quality design for circuits and systems in CMOS technology. He has also proposed many inventions to improve reliability and quality of integrated circuits, generating 125 U.S. patents and 135 Taiwan patents in Taiwan. As an active member of the global IEEE community, he has been Technical Program Committee and Session Chair of numerous international conferences and was selected as the Distinguished Lecturer in IEEE Circuits and Systems Society for year 2006-2007. In 2007 Ker was named IEEE Fellow for his contributions to electrostatic protection in integrated circuits, and performance optimization of VLSI micro-systems. He holds a Ph.D. from the Institute of Electronics, National Chiao-Tung University.

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