Overview

This text discusses architectural and circuit considerations for optimizing the design of oversampled A/D interfaces for mixed-signal CMOS ASICs. The mathematical background is presented and it is suitable for novices in the field. Practical recipes on how to get the maximum performance from these kinds of circuits are presented and illustrated through three converter prototypes in CMOS submicron technologies. A feature of this book is the presentation of a systematic methodology for increasing the productivity of engineers in the design of high-performance modulators. It uses optimization at the architecture and the circuit levels, together with hierarchical transmission of the specifications among levels. The tasks of architecture selection, architecture sizing and building block sizing are supported by CAD tools, thus allowing designers to obtain demanding modulator specifications in short design cycles. The book is organized such that it can be used for a graduate course on S modulator design. In addition, the book is a reference for designers who want to improve their productivity in the design of oversampled mixed-signal interfaces.

Full Product Details

Author:   Fernando Medeiro ,  Belén Pérez Verdú ,  Angel Rodríguez-Vázquez
Publisher:   Springer
Imprint:   Springer
Edition:   1999 ed.
Volume:   480
Dimensions:   Width: 15.60cm , Height: 1.90cm , Length: 23.40cm
Weight:   1.370kg
ISBN:  

9780792383529

ISBN 10:   0792383524
Pages:   287
Publication Date:   30 November 1998
Audience:   College/higher education ,  Professional and scholarly ,  General/trade ,  Undergraduate ,  Postgraduate, Research & Scholarly
Format:   Hardback
Publisher's Status:   Active
Availability:   In Print  
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Table of Contents

1 Introduction.- 2 OVERSAMPLING SIGMA-DELTA A/D CONVERTERS: Basic concepts and state of the art.- 3 Modeling of Error Mechanisms in Sigma-Delta Modulators.- 4 Behavioral Simulation of Sigma-Delta Modulators.- 5 Sdopt+Fridge: Tools for the automatic design of Sigma-Delta modulators.- 6 Integrated Circuit Design (I): A 17-bit 40kSample/s fourth-order cascade Sigma-Delta modulator.- 7 Integrated Circuit Design (II): A 13-bit 2.2MSample/s fourth-order cascade multi-bit Sigma-Delta modulator.- References.- Appendix: Time-domain analysis of low-order ?? modulators.- A.1 Introduction.- A.2 First-Order Modulator.- A.3 Second-Order Modulator.

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