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OverviewTime-interleaved Analog-to-Digital Converters describes the research performed on low-power time-interleaved ADCs. A detailed theoretical analysis is made of the time-interleaved Track & Hold, since it must be capable of handling signals in the GHz range with little distortion, and minimal power consumption. Timing calibration is not attractive, therefore design techniques are presented which do not require timing calibration. The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that the first can consume about 10 times less power than the latter, and this conclusion is supported by literature. Time-interleaved Analog-to-Digital Converters describes the design of a high performance time-interleaved ADC, with much attention for practical design aspects, aiming at both industry and research. Measurements show best-inclass performance with a sample-rate of 1.8 GS/s, 7.9 ENOBs and a power efficiency of 1 pJ/conversion-step. Full Product DetailsAuthor: Simon Louwsma , Ed van Tuijl , Bram NautaPublisher: Springer Imprint: Springer Edition: 2011 ed. Dimensions: Width: 15.50cm , Height: 0.80cm , Length: 23.50cm Weight: 0.454kg ISBN: 9789400799516ISBN 10: 9400799519 Pages: 136 Publication Date: 13 December 2014 Audience: Professional and scholarly , Professional & Vocational Format: Paperback Publisher's Status: Active Availability: Manufactured on demand  We will order this item for you from a manufactured on demand supplier. Table of Contents1. Introduction. – 2. Time-interleaved Track and Holds.- 3. Sub-ADC architectures for time-interleaved ADCs. – 4. Implementation of a high-speed time-interleaved ADC. – 5. Summary and conclusions.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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