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Overview"With vastly increased complexity and functionality in the ""nanometer era"" (i.e. hundreds of millions of transistors on one chip), increasing the performance of integrated circuits has become a challenging task. Connecting effectively (interconnect design) all of these chip elements has become the greatest determining factor in overall performance. 3-D integrated circuit design may offer the best solutions in the near future. This is the first book on 3-D integrated circuit design, covering all of the technological and design aspects of this emerging design paradigm, while proposing effective solutions to specific challenging problems concerning the design of 3-D integrated circuits. A handy, comprehensive reference or a practical design guide, this book provides a sound foundation for the design of 3-D integrated circuits." Full Product DetailsAuthor: Vasilis F. Pavlidis (Assistant Professor, School of Computer Science, University of Manchester, UK) , Eby G. Friedman (Distinguished Professor, Department of Electrical and Computer Engineerin, University of Rochester, Rochester, NY, USA)Publisher: Elsevier Science & Technology Imprint: Morgan Kaufmann Publishers In Dimensions: Width: 19.10cm , Height: 2.80cm , Length: 23.50cm Weight: 0.850kg ISBN: 9780123743435ISBN 10: 0123743435 Pages: 336 Publication Date: 31 October 2008 Audience: Professional and scholarly , Professional & Vocational Replaced By: 9780124105010 Format: Paperback Publisher's Status: Active Availability: Out of stock  The supplier is temporarily out of stock of this item. It will be ordered for you on backorder and shipped when it becomes available. Table of ContentsChapter 1. Introduction Chapter 2. Manufacturing of 3-D Packaged SystemsChapter 3. 3-D Integrated Circuit Fabrication Technologies Chapter 4. Interconnect Prediction Models Chapter 5. Physical Design Techniques for 3-D ICsChapter 6. Thermal Management Techniques Chapter 7. Timing Optimization for Two-Terminal Interconnects Chapter 8. Timing Optimization for Multi-Terminal Interconnects Appendix A: Enumeration of Gate Pairs in a 3-D IC Appendix B: Formal Proof of Optimum Single Via Placement Appendix C: Proof of the Two-Terminal Via Placement HeuristicAppendix D: Proof of Condition for Via Placement of Multi-Terminal Nets ReferencesReviewsAuthor InformationVasilis F. Pavlidis received the B.S. and M.Eng. in electrical and computer engineering from the Democritus University of Thrace, Xanthi, Greece, in 2000 and 2002, respectively. He received the M.Sc. and Ph.D. degrees from, University of Rochester, Rochester, NY in 2003 and 2008, respectively. From 2000 to 2002, he was with INTRACOM S.A., Athens, Greece. In summer of 2007, he was with Synopsys Inc., Mountain View, California. His current research interests are in the area of interconnect modeling, 3-D integration, networks-on-chip, and related design issues in VLSI. Eby G. Friedman received the B.S. degree from Lafayette College in 1979, and the M.S. and Ph.D. degrees from the University of California, Irvine, in 1981 and 1989, respectively, all in electrical engineering. From 1979 to 1991, he was with Hughes Aircraft Company, rising to the position of manager of the Signal Processing Design and Test Department, responsible for the design and test of high performance digital and analog IC's. He has been with the Department of Electrical and Computer Engineering at the University of Rochester since 1991, where he is a Distinguished Professor, the Director of the High Performance VLSI/IC Design and Analysis Laboratory, and the Director of the Center for Electronic Imaging Systems. He is also a Visiting Professor at the Technion - Israel Institute of Technology. His current research and teaching interests are in high performance synchronous digital and mixed-signal microelectronic design and analysis with application to high speed portable processors and low power wireless communications. He is the author of more than 300 papers and book chapters, several patents, and the author or editor of ten books in the fields of high speed and low power CMOS design techniques, high speed interconnect, and the theory and application of synchronous clock and power distribution networks. He was the Editor-in-Chief of the IEEE Transactions on Very Large Scale Integration (VLSI) Systems, a Member of the editorial board of the Proceedings of the IEEE and a recipient of the University of Rochester Graduate Teaching Award, and a College of Engineering Teaching Excellence Award. Dr. Friedman is a Senior Fulbright Fellow and an IEEE Fellow. Tab Content 6Author Website:Countries AvailableAll regions |
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