Overview

""The Synthesis Approach to Digital System Design"" is designed as a reference and a textbook that provides a comprehensive presentation of techniques and algorithms used in high-level description, synthesis and verification. By using a complete, high-level design system as a vehicle for the text, the authors cover a number of the key aspects of high-level design methods as well as the basic algorithms and data structures that support them. The text aims to serve as a starting point for the developers of new high-level design aids and for potential users of such systems as well.

Full Product Details

Author:   Petra Michel ,  Ulrich Lauther ,  Peter Duzy
Publisher:   Springer
Imprint:   Springer
Edition:   1992 ed.
Volume:   170
Dimensions:   Width: 15.50cm , Height: 2.30cm , Length: 23.50cm
Weight:   1.730kg
ISBN:  

9780792391999

ISBN 10:   0792391993
Pages:   415
Publication Date:   31 March 1992
Audience:   College/higher education ,  Professional and scholarly ,  Postgraduate, Research & Scholarly ,  Professional & Vocational
Format:   Hardback
Publisher's Status:   Active
Availability:   In Print  
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Table of Contents

Foreword.- Acknowledgements.- 1 Introduction to Synthesis.- 1.1 The Y-Chart—Levels and Domains of Description.- 1.2 Design Flow and Taxonomy of Synthesis.- 1.3 Entry Points and User Interfaces.- 1.4 Validation.- 1.5 Testing.- 2 Hardware Description Languages and their Relevance to Synthesis.- 2.1 Introduction.- 2.2 VHDL Example- Bar-Code Preprocessor.- 2.3 VHDL Hardware Description Language.- 2.4 Relevance of HDLs to Synthesis.- 2.5 Outlook.- 2.6 Problems for the Reader.- 3 Logic-Level Synthesis.- 3.1 Introduction.- 3.2 Preliminaries and Definitions.- 3.3 Minimization of Two-Level Logic.- 3.4 Optimization of Multi-Level Logic.- 3.5 Outlook.- 3.6 Problems for the Reader.- 4 Technology Mapping.- 4.1 Introduction.- 4.2 Abstraction of Technology.- 4.3 Logic-Level Technology Mapping.- 4.4 Register-Transfer Level Technology Mapping.- 4.5 Outlook.- 4.6 Problems for the Reader.- 5 Register-Transfer Level Synthesis.- 5.1 Introduction.- 5.2 Data Path Synthesis.- 5.3 Controller Synthesis.- 5.4 Outlook.- 5.5 Problems for the Reader.- 6 High-Level Synthesis.- 6.1 Introduction.- 6.2 Internal Representation.- 6.3 Synthesis of the Register-Transfer Level Structure.- 6.4 Scheduling.- 6.5 Allocation and Assignment Tasks.- 6.6 Outlook.- 6.7 Problems for the Reader.- 7 System-Level Synthesis.- 7.1 Introduction.- 7.2 System-Level Partitioning.- 7.3 Behavioral Transformations.- 7.4 Synthesizing from System-Level Descriptions.- 7.5 Outlook.- 8 Formal Methods for Synthesis.- 8.1 Introduction.- 8.2 Formal Reasoning about Digital Systems.- 8.3 Interactive, Formal Synthesis.- 8.4 Formally Verified Synthesis Functions.- 8.5 Outlook.- 8.6 Problems for the Reader.- 9 Synthesis Related Aspects of Simulation.- 9.1 Introduction.- 9.2 Multi-Level Modeling.- 9.3 Simulation Techniques.- 9.4 Multi-LevelSimulation.- 9.5 Outlook.- 9.6 Problems for the Reader.- 10 Synthesis Related Aspects in Testing.- 10.1 Introduction.- 10.2 General Testability Aspects.- 10.3 Test Objects in Synthesis.- 10.4 Test Methods for Synthesis.- 10.5 Test Data Generation.- 10.6 Outlook.- 10.7 Problems for the Reader.

Reviews

'I wholeheartedly recommend the use of this text in all high-level design aids and for all users of such system.' Microprocessors and Microsystems 18: 8 1994

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