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OverviewThis book tackles head-on the challenges of digital design in the era of billion-transistor SoCs. It discusses fundamental design concepts in design and coding required to produce robust, functionally correct designs. It also provides specific techniques for measuring and minimizing complexity in RTL code. Finally, it discusses the tradeoff between RTL and high-level (C-based) design and how tools and languages must progress to address the needs of tomorrow’s SoC designs. Full Product DetailsAuthor: Michael Keating, Synopsys FellowPublisher: Springer-Verlag New York Inc. Imprint: Springer-Verlag New York Inc. Dimensions: Width: 15.50cm , Height: 2.00cm , Length: 23.50cm Weight: 0.547kg ISBN: 9781441985859ISBN 10: 1441985859 Pages: 234 Publication Date: 19 May 2011 Audience: Professional and scholarly , Professional & Vocational Format: Hardback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of ContentsReviewsAuthor InformationMike Keating is a Synopsys Fellow. Over the last 12 years, he has been with Synopsys focusing on IP development methodology, hardware and software design quality and low power design. His current research focuses on high level design and the challenges of designing extremely complex systems. Mike received his BSEE and MSEE from Stanford University, and has over 25 years experience in ASIC and system design. He is co-author of the Reuse Methodology Manual and the Low Power Methodology Manual. In 2007, ISQED gave Mike the Quality Award for contributions to quality in electronic design. Tab Content 6Author Website:Countries AvailableAll regions |
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