The Simple Art of SoC Design: Closing the Gap between RTL and ESL

Author:   Michael Keating, Synopsys Fellow
Publisher:   Springer-Verlag New York Inc.
Edition:   2011 ed.
ISBN:  

9781489998163


Pages:   234
Publication Date:   01 October 2014
Format:   Paperback
Availability:   Manufactured on demand   Availability explained
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The Simple Art of SoC Design: Closing the Gap between RTL and ESL


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Overview

This book tackles head-on the challenges of digital design in the era of billion-transistor SoCs. It discusses fundamental design concepts in design and coding required to produce robust, functionally correct designs. It also provides specific techniques for measuring and minimizing complexity in RTL code. Finally, it discusses the tradeoff between RTL and high-level (C-based) design and how tools and languages must progress to address the needs of tomorrow’s SoC designs.

Full Product Details

Author:   Michael Keating, Synopsys Fellow
Publisher:   Springer-Verlag New York Inc.
Imprint:   Springer-Verlag New York Inc.
Edition:   2011 ed.
Dimensions:   Width: 15.50cm , Height: 1.30cm , Length: 23.50cm
Weight:   0.391kg
ISBN:  

9781489998163


ISBN 10:   1489998160
Pages:   234
Publication Date:   01 October 2014
Audience:   Professional and scholarly ,  Professional & Vocational
Format:   Paperback
Publisher's Status:   Active
Availability:   Manufactured on demand   Availability explained
We will order this item for you from a manufactured on demand supplier.

Table of Contents

The Challenges of Complex Design; Simplifying RTL Design; Reducing Complexity in Control-Dominated Designs; Hierarchical State Machines; More on State Space; Verification; Reducing Complexity in Data Path Dominated Designs; Simplifying Interfaces; Complexity at the Chip Level; Raising Abstraction Above RTL; SystemVerilog Extensions; The Future of Design.

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Author Information

Mike Keating is a Synopsys Fellow. Over the last 12 years, he has been with Synopsys focusing on IP development methodology, hardware and software design quality and low power design. His current research focuses on high level design and the challenges of designing extremely complex systems. Mike received his BSEE and MSEE from Stanford University, and has over 25 years experience in ASIC and system design. He is co-author of the Reuse Methodology Manual and the Low Power Methodology Manual. In 2007, ISQED gave Mike the Quality Award for contributions to quality in electronic design.

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