Testing Static Random Access Memories: Defects, Fault Models and Test Patterns

Author:   Said Hamdioui
Publisher:   Springer-Verlag New York Inc.
Edition:   Softcover reprint of the original 1st ed. 2004
Volume:   26
ISBN:  

9781441954305


Pages:   221
Publication Date:   09 December 2010
Format:   Paperback
Availability:   Out of stock   Availability explained
The supplier is temporarily out of stock of this item. It will be ordered for you on backorder and shipped when it becomes available.

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Testing Static Random Access Memories: Defects, Fault Models and Test Patterns


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Overview

Testing Static Random Access Memories covers testing of one of the important semiconductor memories types; it addresses testing of static random access memories (SRAMs), both single-port and multi-port. It contributes to the technical acknowledge needed by those involved in memory testing, engineers and researchers. The book begins with outlining the most popular SRAMs architectures. Then, the description of realistic fault models, based on defect injection and SPICE simulation, are introduced. Thereafter, high quality and low cost test patterns, as well as test strategies for single-port, two-port and any p-port SRAMs are presented, together with some preliminary test results showing the importance of the new tests in reducing DPM level. The impact of the port restrictions (e.g., read-only ports) on the fault models, tests, and test strategies is also discussed. Features: -Fault primitive based analysis of memory faults, -A complete framework of and classification memory faults, -A systematic way to develop optimal and high quality memory test algorithms, -A systematic way to develop test patterns for any multi-port SRAM, -Challenges and trends in embedded memory testing.

Full Product Details

Author:   Said Hamdioui
Publisher:   Springer-Verlag New York Inc.
Imprint:   Springer-Verlag New York Inc.
Edition:   Softcover reprint of the original 1st ed. 2004
Volume:   26
Dimensions:   Width: 15.50cm , Height: 1.30cm , Length: 23.50cm
Weight:   0.454kg
ISBN:  

9781441954305


ISBN 10:   1441954309
Pages:   221
Publication Date:   09 December 2010
Audience:   Professional and scholarly ,  Professional & Vocational
Format:   Paperback
Publisher's Status:   Active
Availability:   Out of stock   Availability explained
The supplier is temporarily out of stock of this item. It will be ordered for you on backorder and shipped when it becomes available.

Table of Contents

I Introductory.- 1 Introduction.- 2 Semiconductor memory architecture.- 3 Space of memory faults.- 4 Preparation for circuit simulation.- II Testing single-port and two-port SRAMs.- 5 Experimental analysis of two-port SRAMs.- 6 Tests for single-port and two-port SRAMs.- 7 Testing restricted two-port SRAMs.- III Testing p-port SRAMs.- 8 Experimental analysis of p-port SRAMs.- 9 Tests for p-port SRAMs.- 10 Testing restricted p-port SRAMs.- 11 Trends in embedded memory testing.- A Simulation results for two-port SRAMs.- A.1 Simulation results for opens.- A.2 Simulation results for shorts.- A.3 Simulation results for bridges.- B Simulation results for three-port SRAMs.- B.1 Simulation results for opens and shorts.- B.2 Simulation results for bridges.

Reviews

From the reviews: Static random access memories (SRAMs) enjoy a strategic position in the microelectronic industry. ! This book concentrates on the study of fault modeling, testing and test strategies for SRAMs. ! The book provides a well-written coverage in the area of single-, two- and n-port SRAM testing, fault modeling, and simulation. It is well-organized and very timely. ! The book promises to make valuable contribution to the education of graduate students ! . I highly recommend this book ! . (Mile Stojcev, Microelectronics Reliability, Vol. 45, 2005)


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