Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits

Author:   Sandeep K. Goel ,  Krishnendu Chakrabarty
Publisher:   Taylor & Francis Inc
Volume:   19
ISBN:  

9781439829417


Pages:   259
Publication Date:   25 October 2013
Format:   Hardback
Availability:   In Print   Availability explained
This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us.

Our Price $410.00 Quantity:  
Add to Cart

Share |

Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits


Add your own review!

Overview

Advances in design methods and process technologies are causing a continuous increase in the complexity of integrated circuits (ICs). However, the increased complexity and nanometer-size features of modern ICs make them susceptible to manufacturing defects, as well as performance and quality issues. This book covers common problems in areas such as process variation, power supply, noise, crosstalk, resistive opens/bridges, and design-for-manufacturing (DiM)-related rule violations. The book also addresses small-delay defects (SDDs) and testing, which can cause immediate failures if introduced on both critical and non-critical paths in the circuit.

Full Product Details

Author:   Sandeep K. Goel ,  Krishnendu Chakrabarty
Publisher:   Taylor & Francis Inc
Imprint:   CRC Press Inc
Volume:   19
Weight:   0.589kg
ISBN:  

9781439829417


ISBN 10:   1439829411
Pages:   259
Publication Date:   25 October 2013
Audience:   College/higher education ,  General/trade ,  Tertiary & Higher Education ,  General
Format:   Hardback
Publisher's Status:   Active
Availability:   In Print   Availability explained
This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us.

Table of Contents

Fundamentals of Small-Delay Defect Testing. Timing-Aware ATPG: K Longest Paths. Timing-Aware ATPG. Faster-than-At-Speed: Faster-than-at-Speed Test for Screening Small-Delay Defects. Circuit Path Grading Considering Layout, Process Variations, and Cross Talk. Alternative Methods: Output Deviations-Based SDD Testing. Hybrid/Top-off Test Pattern Generation Schemes for Small-Delay Defects. Circuit Topology-Based Test Pattern Generation for Small-Delay Defects. SDD Metrics: Small-Delay Defect Coverage Metrics. Conclusion. References.

Reviews

Author Information

Sandeep Kumar Goel received the B. Tech. degree from the Institute of Engineering and Tec1ul0logy, Lucknow, in 1998, the M. Tech. degree from the Indian Institute of Technology, Delhi, in 1999, and the Ph.D. degree from the University of Twente, Enschede, Netherlands, in 2005. He is currently a principal engineer at LSI, Milpitas, California. He is a senior member of the IEEE. Krishnendu Chakrabarty received the B. Tech. degree from the Indian Institute of Technology, Kharagpur, in 1990, as well as M.S.E. and Ph.D. degrees from the University of Michigan, Ann Arbor, in 1992 and 1995, respectively. He is now Professor of Electrical and Computer Engineering at Duke University. He is also a Chair Professor of Software Theory in the School of Software, Tsinghua University, Beijing, China. Dr. Chakrabarty is a recipient of the National Science Foundation Early Faculty (CAREER) award, the Office of Naval Research Young Investigator award, the Humboldt Research Fellowship, and several best papers awards at IEEE conferences.

Tab Content 6

Author Website:  

Customer Reviews

Recent Reviews

No review item found!

Add your own review!

Countries Available

All regions
Latest Reading Guide

lgn

al

Shopping Cart
Your cart is empty
Shopping cart
Mailing List