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OverviewThe rapid evolution and explosive growth of integrated circuit technology have had a profound effect on society. Integrated circuits (ICs) are used universally and the expanding use of IC technology requires more accurate circuit analysis methods and tools, prompting the introduction of computers into the design process. The goal of this book is to build a firm foundation in the use of computer-assisted techniques for IC device and process design. Both practical and analytical viewpoints are stressed to give the reader the background necessary to appreciate CAD tools and to feel comfortable with their use. This work presents a discourse on process and device CAD as interrelated subjects, building on a wide range of experiences and applications of the SUPREM program. Chapter 1 focuses on the motivation for coupled process and device CAD. In Chapter 2 SUPREM III is introduced, and process CAD is discussed in terms of ion-implantation, impurity diffusion, and oxidation models. Chapter 3 introduces the Stanford device analysis program SEDAN III (SEmiconductor Device ANalysis). The next three chapters move into greater detail concerning device operating principles and analysis techniques. Chapter 4 reviews the classical formulation of pn junction theory and uses device analysis (SEDAN) both to evaluate some of the classical assumptions and to investigate the difficult problem of high level injection. Chapter 5 returns to MOS devices, reviews the first-order MOS theory, and introduces some important second-order effects. Chapter 6 considers the bipolar transistor. Chapter 7 considers the application of process simulation and device analysis to technology design. The BiCMOS process is selected as a useful design vehicle for two reasons. Firstly, it allows the reader to pull together concepts from the entire book and secondly, the inherent nature of BiCMOS technology offers real constraints and hence trade-offs which must be understood and accounted for. Full Product DetailsAuthor: Robert W. Dutton , Zhiping YuPublisher: Springer Imprint: Springer Edition: 1993 ed. Volume: 243 Dimensions: Width: 15.50cm , Height: 2.20cm , Length: 23.50cm Weight: 1.610kg ISBN: 9780792393795ISBN 10: 0792393791 Pages: 373 Publication Date: 31 July 1993 Audience: Professional and scholarly , Professional & Vocational Format: Hardback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of Contents1 Technology-Oriented CAD.- 1.1 Introduction.- 1.2 Process and Device CAD.- 1.3 Process Simulation Techniques.- 1.4 Interfaces in Process and Device CAD.- 1.5 CMOS Technology.- 1.6 Summary.- 1.7 Exercises.- 1.8 References.- 2 Introduction to SUPREM.- 2.1 Introduction.- 2.2 Ion Implantation.- 2.3 Oxidation.- 2.4 Impurity Diffusion.- 2.5 Summary.- 2.6 Exercises.- 2.7 References.- 3 Device CAD.- 3.1 Introduction.- 3.2 Semiconductor Device Analysis.- 3.3 Field-Effect Structures.- 3.4 Bipolar Junction Structures.- 3.5 Summary.- 3.6 Exercises.- 3.7 References.- 4 PN Junctions.- 4.1 Introduction.- 4.2 Carrier Densities: Equilibrium Case.- 4.3 Non-Equilibrium.- 4.4 Carrier Transport and Conservation.- 4.5 The pn Junction — Equilibrium Conditions.- 4.6 The pn Junction — Non-equilibrium.- 4.7 SEDAN Analysis.- 4.8 Summary.- 4.9 Exercises.- 4.10 References.- 5 MOS Structures.- 5.1 Introduction.- 5.2 The MOS Capacitor.- 5.3 Basic MOSFET I-V Characteristics.- 5.4 Threshold Voltage in Nonuniform Substrate.- 5.5 MOS Device Design by Simulation.- 5.6 Summary.- 5.7 Exer cises.- 5.8 References.- 6 Bipolar Transistors.- 6.1 Introduction.- 6.2 Lateral pnp Transistor Operation.- 6.3 Transport Current Analysis.- 6.4 Generalized Charge Storage Model.- 6.5 Transistor Equivalent Circuits.- 6.6 Second Order Effects.- 6.7 Transit Time and Cutoff Frequency.- 6.8 Application of Simulation Tools.- 6.9 Summary.- 6.10 Exercises.- 6.11 References.- 7 BiCMOS Technology.- 7.1 Introduction.- 7.2 Triple-Diffused BiCMOS.- 7.3 Buried-Epitaxial Layer BiCMOS.- 7.4 Summary.- 7.5 Exercises.- 7.6 References.- A Numerical Analyis.- B BiCMOS Technology Overview.- C Templates for PISCES Simulation.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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