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OverviewThis book is an A-Z guide to using SystemVerilog for ASIC design, from conception to RTL coding, to synthesis and verification. Readers will benefit from a thorough introduction to the powerful constructs and features of SystemVerilog. In addition, the verification methodology of Universal Verification Methodology (UVM) is used to build test-benches that allow for verification of complicated designs and synthesis basics are discussed, using the Synopsys Design Compiler (DC). To complete this book's package as a practical guide, readers are introduced to the fundamentals of static timing analysis. Full Product DetailsAuthor: Mark A. AzadpourPublisher: Springer-Verlag New York Inc. Imprint: Springer-Verlag New York Inc. Edition: 2015 ed. ISBN: 9781461417576ISBN 10: 1461417570 Pages: 300 Publication Date: 01 December 2015 Audience: Professional and scholarly , Professional & Vocational Format: Hardback Publisher's Status: Active Availability: In stock  We have confirmation that this item is in stock with the supplier. It will be ordered in for you and dispatched immediately. Table of ContentsThe SystemVerilog language.- Designing with SystemVerilog.- Verification with SytemVerilog.- Building environment and the DUT.- Synthesis.- Timing analysis.ReviewsAuthor InformationMark A. Aazadpour is a senior staff member at Seagate Technology, LLC. Tab Content 6Author Website:Countries AvailableAll regions |
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