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OverviewSystem-On-a-Chip Verification: Methodology and Techniques is the first book to cover verification strategies and methodologies for SOC verification from system level verification to the design sign- off. The topics covered include Introduction to the SOC design and verification aspects, System level verification in brief, Block level verification, Analog/mixed signal simulation, Simulation, HW/SW Co-verification, Static netlist verification, Physical verification, and Design sign-off in brief. All the verification aspects are illustrated with a single reference design for Bluetooth application. System-On-a-Chip Verification: Methodology and Techniques takes a systematic approach that covers the following aspects of verification strategy in each chapter: Explanation of the objective involved in performing verification after a given design step; Features of options available; When to use a particular option; How to select an option; and Limitations of the option. This exciting new book will be of interest to all designers and test professionals. Full Product DetailsAuthor: Prakash Rashinkar , Peter Paterson , Leena SinghPublisher: Springer-Verlag New York Inc. Imprint: Springer-Verlag New York Inc. Edition: Softcover reprint of the original 1st ed. 2001 Dimensions: Width: 15.50cm , Height: 2.10cm , Length: 23.50cm Weight: 0.605kg ISBN: 9781475774689ISBN 10: 1475774680 Pages: 372 Publication Date: 23 April 2013 Audience: Professional and scholarly , Professional & Vocational Format: Paperback Publisher's Status: Active Availability: Manufactured on demand  We will order this item for you from a manufactured on demand supplier. Table of ContentsSystem-level Verification.- Block-level Verification.- Analog/Mixed Signal Simulation.- Simulation.- Hardware/Software Co-verification.- Static Netlist Verification.- Physical Verification and Design Sign-off.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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