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OverviewFull Product DetailsAuthor: Lauren Guckert (Performance Engineer, ARM Inc., Austin, Texas, USA) , Earl E. Swartzlander (Professor of Electrical and Computer Engineering, University of Texas, Austin, USA)Publisher: Institution of Engineering and Technology Imprint: Institution of Engineering and Technology ISBN: 9781785615610ISBN 10: 1785615610 Pages: 368 Publication Date: 01 May 2018 Audience: Professional and scholarly , Professional & Vocational Format: Hardback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of ContentsChapter 1: Introduction Chapter 2: Memristor logic gates Chapter 3: Adder arithmetic units Chapter 4: Multiplier arithmetic units Chapter 5: Divider arithmetic units Chapter 6: Memristor-based adder designs Chapter 7: Memristor-based multiplier designs Chapter 8: Memristor-based divider designs Chapter 9: Proposed future work Chapter 10: ConclusionReviewsAuthor InformationLauren Guckert received her PhD from the University of Texas in computer engineering in 2016. She now works as a Performance Engineer at Arm Ltd. in Austin, Texas, USA where she focuses on performance analysis for state-of-the-art system IP designs. Earl Swartzlander is a Professor of Electrical and Computer Engineering at the University of Texas at Austin, USA. He conducts research in computer engineering with emphasis on application-specific processor design, including high-speed computer arithmetic, embedded processor architecture, VLSI technology, and nanotechnology. Tab Content 6Author Website:Countries AvailableAll regions |
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