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Overviewiming, timing, timing! That is the main concern of a digital designer charged with designing a semiconductor chip. What is it, how is it T described, and how does one verify it? The design team of a large digital design may spend months architecting and iterating the design to achieve the required timing target. Besides functional verification, the t- ing closure is the major milestone which dictates when a chip can be - leased to the semiconductor foundry for fabrication. This book addresses the timing verification using static timing analysis for nanometer designs. The book has originated from many years of our working in the area of timing verification for complex nanometer designs. We have come across many design engineers trying to learn the background and various aspects of static timing analysis. Unfortunately, there is no book currently ava- able that can be used by a working engineer to get acquainted with the - tails of static timing analysis. The chip designers lack a central reference for information on timing, that covers the basics to the advanced timing veri- cation procedures and techniques. Full Product DetailsAuthor: J. Bhasker , Rakesh Chadha , Rakesh ChadhaPublisher: Springer-Verlag New York Inc. Imprint: Springer-Verlag New York Inc. Edition: 2009 ed. Dimensions: Width: 15.50cm , Height: 3.00cm , Length: 23.50cm Weight: 0.896kg ISBN: 9781441947154ISBN 10: 1441947159 Pages: 572 Publication Date: 08 September 2011 Audience: Professional and scholarly , Professional & Vocational Format: Paperback Publisher's Status: Active Availability: Awaiting stock  The supplier is currently out of stock of this item. It will be ordered for you and placed on backorder. Once it does come back in stock, we will ship it out for you. Table of ContentsReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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