Overview

The process of designing large real-time embedded signal processing systems is plagued by a lack of coherent specification and design methodology. A canonical waterfall design process is commonly used to specify, design, and implement these systems with commercial-off-the-shelf (COTS) multiprocessing (MP) hardware and software. Powerful frameworks exist for each individual phase of this canonical design process, but no single methodology exists which enables these frameworks to work together coherently, that is, allowing the output of a framework used in one phase to be consumed by a different framework used in the next phase. This lack of coherence usually leads to design errors that are not caught until well into the implementation phase. The cost of redesign increases as the design moves through these three stages, thus, the methodology desccribed above can become costly if errors are not detected in the early stages of design. This text shows how designs targeting COTS MP technologies can be improved by providing a coherent coupling between these frameworks, a quality known as ""model continuity"". This book presents a new specification and design methodology (SDM) which accomplishes the requirements specification, design exploration, and implementation of COTS MP-based signal processing systems by using powerful commercial frameworks that are intelligently integrated into a single domain-specific SDM.

Full Product Details

Author:   Randall S. Janka
Publisher:   Springer
Imprint:   Springer
Edition:   2002 ed.
Dimensions:   Width: 15.50cm , Height: 1.50cm , Length: 23.50cm
Weight:   1.200kg
ISBN:  

9780792376262

ISBN 10:   0792376269
Pages:   221
Publication Date:   30 November 2001
Audience:   College/higher education ,  Professional and scholarly ,  Postgraduate, Research & Scholarly ,  Professional & Vocational
Format:   Hardback
Publisher's Status:   Active
Availability:   In Print  
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Table of Contents

1 Introduction.- 1.1 The Basic Problem.- 1.2 A Solution to the Problem.- 1.3 Contributions.- 1.4 Organization.- 1.5 Convergence of Research Threads.- 2 Problem Background.- 2.1 Background.- 2.2 The Domain-Specific Problem.- 2.3 A Domain-Specific Solution.- 3 System Requirements & Intrinsic SDM Assessment.- 3.1 System Requirements Specification Domains.- 3.2 Domain-Relevant Models of Computation.- 3.3 Best MOCs for Domain-Specific Specification Axes.- 3.4 Implicit Framework MOCs.- 3.5 Comparing the Monolithic Frameworks.- 4 Quantified Extrinsic SDM Assessment.- 4.1 A Unified Specification-Modeling Methodology Evaluation Framework.- 4.2 Quantification of Sarkar Basis.- 4.3 Using Quantified Basis to Characterize CASE SDM Frameworks.- 4.4 Conclusion.- 5 Extending Gajski’s SER Methodology.- 5.1 Background.- 5.2 Parallels between Gajski’s SER & Our ADoI.- 5.3 Extending Gajski’s SER to Our ADoI.- 6 The Magic Specification & Design Methodology.- 6.1 Overview of the MAGIC Methodology.- 6.2 Establishing Model Continuity.- 6.3 “Rules”—The Steps of the MAGIC SDM.- 6.4 “Tools”—The Frameworks Integrated into the MAGIC SDM.- 6.5 Model Continuity via Middleware.- 7 Case Study: Validating the Magic SDM Using A Sar Processor Application.- 7.1 RASSP SAR Benchmark Overview.- 7.2 Tabulate Requirements.- 7.3 Capture Non-Constraint Requirements in an Executable Model.- 7.4 Build Executable Workbook with Requirements.- 7.5 Gather Benchmarks for Tokens.- 7.6 Explore Alternative Architectures & Technologies.- 7.7 Make Design Decisions.- 7.8 Create Implementation Specification.- 7.9 Difficulties Encountered & Overcome.- 7.10 Conclusion.- 8 Magic Quantification & Summary.- 8.1 Model continuity in the MAGIC SDM.- 8.2 Sarkar Quantification of MAGIC SDM.- 8.3 Summary.- 9 Conclusion:Directions for Further Research & Applying Magic to Soc Domain.- 9.1 Applied & Basic Research.- 9.2 Applying MAGIC Concepts to the SoC Domain.- 9.3 Virtual Component Codesign (VCC).- 9.4 Codesign vis à vis Coverification.- 9.5 Concluding Comments.- Appendix A: Details of Vsbpl & MPI Middleware.- A. 1 VSIPL: Computation Middleware.- A.2 MPI: Communications Middleware.- Appendix B: Details of Case Study.- B.1 Simulink Details.- B.2 VSIPL Code Generation Subtleties.- B.3 eArchitect Details.- References.

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