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OverviewThis book focusses on the spacer engineering aspects of novel MOS-based device–circuit co-design in sub-20nm technology node, its process complexity, variability, and reliability issues. It comprehensively explores the FinFET/tri-gate architectures with their circuit/SRAM suitability and tolerance to random statistical variations. Full Product DetailsAuthor: Sudeb Dasgupta , Brajesh Kumar Kaushik (Indian Institute of Technology Roorkee, Uttareakhand, India) , Pankaj Kumar Pal (Indian Institute of Technology-Roorkee, India)Publisher: Taylor & Francis Ltd Imprint: CRC Press Weight: 0.453kg ISBN: 9780367573553ISBN 10: 0367573555 Pages: 138 Publication Date: 30 June 2020 Audience: College/higher education , General/trade , Tertiary & Higher Education , General Format: Paperback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of ContentsReviewsAuthor InformationSudeb Dasgupta, Brajesh Kumar Kaushik, Pankaj Kumar Pal Tab Content 6Author Website:Countries AvailableAll regions |
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