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OverviewMarket demand for microprocessor performance has motivated continued scaling of CMOS through a succession of lithography generations. Quantum mechanical limitations to continued scaling are becoming readily apparent. Partially Depleted Silicon-on-Insulator (PD-SOI) technology is emerging as a promising means of addressing these limitations. It also introduces additional design complexity which must be well understood. This text first introduces the student or practising engineer to SOI device physics and its fundamental idiosyncrasies. It then walks the reader through realizations of these mechanisms which are observed in common high-speed microprocessor designs. Rules of thumb and comparisons to conventional bulk CMOS are offered to guide implementation. SOI's ultimate advantage, however, may lie in the unique circuit topologies it supports; a number of these novel new approaches is also described. Full Product DetailsAuthor: Kerry Bernstein , Norman J. RohrerPublisher: Springer Imprint: Springer Edition: 2000 ed. Dimensions: Width: 15.60cm , Height: 1.40cm , Length: 23.40cm Weight: 1.150kg ISBN: 9780792377627ISBN 10: 0792377621 Pages: 222 Publication Date: 31 January 2000 Audience: College/higher education , Professional and scholarly , Undergraduate , Postgraduate, Research & Scholarly Format: Hardback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of ContentsThe Time for SOI.- SOI Device Structures.- SOI Device Electrical Properties.- Static Circuit Design Response.- Dynamic Circuit Design Considerations.- SRAM Cache Design Considerations.- Specialized Function Circuits in SOI.- Global Chip Design Considerations.- Future Oppurtunities in SOI.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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