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OverviewSystem-on-a-Chip (SOC) integrated circuits composed of embedded cores are now commonplace. Nevertheless, there remain several roadblocks to rapid and efficient system integration. Test development is seen as a major bottleneck in SOC design and manufacturing capabilities. Testing SOCs is especially challenging in the absence of standardized test structures, test automation tools, and test protocols. In addition, long interconnects, high density, and high-speed designs lead to new types of faults involving crosstalk and signal integrity. SOC (System-on-a-Chip) Testing for Plug and Play Test Automation is an edited work containing thirteen contributions that address various aspects of SOC testing. SOC (System-on-a-Chip) Testing for Plug and Play Test Automation, originally published as Volume 18, Issues 4 and 5, of the Journal of Electronic Testing, is a valuable reference for researchers and students interested in various aspects of SOC testing. Full Product DetailsAuthor: Krishnendu ChakrabartyPublisher: Springer-Verlag New York Inc. Imprint: Springer-Verlag New York Inc. Edition: New edition Volume: 21 Dimensions: Width: 21.00cm , Height: 1.20cm , Length: 27.90cm Weight: 1.380kg ISBN: 9781402072055ISBN 10: 1402072058 Pages: 200 Publication Date: 30 September 2002 Audience: College/higher education , Undergraduate Format: Hardback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of ContentsOverview.- On IEEE P1500’s Standard for Embedded Core Test.- Test Planning, Access and Scheduling.- An Integrated Framework for the Design and Optimization of SOC Test Solutions.- On Concurrent Test of Core-Based SOC Design.- A Novel Reconfigurable Wrapper for Testing of Embedded Core-Based SOCs and its Associated Scheduling Algorithm.- The Role of Test Protocols in Automated Test Generation for Embedded-Core-Based System ICs.- CAS-BUS: A Test Access Mechanism and a Toolbox Environment for Core-Based System Chip Testing.- An Integrated Approach to Testing Embedded Cores and Interconnects Using Test Access Mechanism (TAM) Switch.- Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores.- Test Data Compression.- Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor.- Diagnostic Data Compression Techniques for Embedded Memories with Built-In Self-Test.- Interconnect, Crosstalk and Signal Integrity.- Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores.- Signal Integrity: Fault Modeling and Testing in High-Speed SoCs.- On-Chip Clock Faults’ Detector.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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