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OverviewSimultaneous Switching Noise (SSN) of CMOS Devices and Systems covers recent research on package-induced noise problems in single and multi-chip package assemblies. It examines in detail the methods for calculating SSN and overall noise containment in a system. In addition, the authors discuss SSN models and algorithms and a SSN Simulator (SSNS) to calculate the maximum SSN and/or the minimum number of power/ground bon-pad/package-pin connections required for a given system design. These algorithms are extremely powerful in calculating SSN for a large number of output drivers switching simultaneously. Design, package and system engineers will find specific information on a number of important topics and techniques. Among these are: . Detailed methods of modeling chip-package interface parasitics; . SSN modeling for CMOS-based systems, including the negative feedback effects; . Model development and time-domain signal integrity simulations for signal conductors over a perforated and/or noisy reference plane; . Total noise budgeting and dynamic noise immunity study for receivers; . Custom CMOS output driver design techniques to minimize package-induced noise. The result and techniques presented in Simultaneous Switching Noise of CMOS Devices and Systems will be useful both to experienced engineers in packaging and systems areas and also to students entering these field. It will serve as an excellent reference and as a text for advanced courses in CMOS systems design and/or electronic packaging. This book is the first in a new sub-series within SECS. The sub-series is entitled 'Electronic Packaging and Interconnects', and the consulting editor is John L. Prince of the University of Arizona. Full Product DetailsAuthor: Ramesh Senthinathan , John L. PrincePublisher: Springer Imprint: Springer Edition: 1994 ed. Volume: 249 Dimensions: Width: 15.50cm , Height: 1.40cm , Length: 23.50cm Weight: 1.110kg ISBN: 9780792394006ISBN 10: 0792394003 Pages: 205 Publication Date: 30 November 1993 Audience: College/higher education , Professional and scholarly , Undergraduate , Postgraduate, Research & Scholarly Format: Hardback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of Contents1 — Introduction.- 1.1 Background.- 1.2 Introduction.- 2 — Packaged/Scaled CMOS Devices.- 2.1 Introduction.- 2.2 Interconnect Scaling.- 2.3 Delays with Driver/Interconnect Scaling.- 2.4 Summary.- 3 — Methods of Calculating Simultaneous Switching Noise.- 3.1 Introduction.- 3.2 Theory and Modeling.- 3.3 Ground Noise and Vss Pad-Pin Connection Calculation..- 3.4 Results.- 3.5 Behavior of Simultaneous Switching Noise with Scaling..- 3.6 Summary.- 4 — Power Distribution Inductance Modeling.- 4.1 Introduction.- 4.2 Mathematical Formulation of UALGRL.- 4.3 Effective Inductance “Lvss” Modeling.- 4.4 Reference Plane Inductance Network Calculation..- 4.5 Results.- 4.6 Summary.- 5 — Signal Conductors over a Perforated Reference Plane.- 5.1 Introduction.- 5.2 Impact of Reference Plane Openings for Stripline Geometries.- 5.3 Connector Characterization Using S—Parameter Measurement Techniques.- 5.4 Modeling Using Two Dimensional (TEM) Approximation.- 5.5 Three—Dimensional Modeling Technique.- 5.6 Comparison Between Measurement and Simulations..- 5.7 Full—Wave Analysis of a Periodically Perforated Structure.- 5.8 Summary.- 6 — Dynamic Noise Immunity, and Skewing/Damping SSN Waveform.- 6.1 Introduction.- 6.2 Driver Switching Noise and Receiver Noise Immunity.- 6.3 Effects of Skewing Output Drivers.- 6.4 Trade—offs in Using Damping Resistors.- 6.5 Summary.- 7 — Application Specific Output Drivers to Reduce SSN.- 7.1 Introduction.- 7.2 CMOS Output Driver Switching Current Components.- 7.3 Current Controlled Output Drivers.- 7.4 Controlled Slew Rate Output Drivers.- 7.5 Summary.- 8 — SSN Simulator Architecture.- 8.1 Introduction.- 8.2 SSNS Architecture.- 8.3 “Less” Modeling for MCM Vss Connections.- 8.4 Simultaneous Switching Noise Calculation for CMOS MCM123 8.5 Summary.- 9 — Signal Conductors over a Noisy Reference Plane.- 9.1 Introduction and Motivation.- 9.2 Equivalent Electrical Circuit Model Formulation.- 9.3 Calculation of Lumped Circuit Elements.- 9.4 Transient Response Simulations.- 9.5 Impact of Vss Package—Pin Placement on Noise Modeling.- 9.6 Summary.- 10 — Conclusions.- 11 — Discussion and Future Work.- 11.1 BiCMOS Outputs Simultaneous Switching Noise...- 11.2 Use of Substrate-Taps to Reduce SSN.- 11.3 SSNS Architecture Improvement.- Appendix A.- Appendix B.- Appendix C.- Appendix D.- Appendix E.- References.- About the Authors.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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