Overview

This book provides a single-source reference to routing algorithms for Networks-on-Chip (NoCs), as well as in-depth discussions of advanced solutions applied to current and next generation, many core NoC-based Systems-on-Chip (SoCs). After a basic introduction to the NoC design paradigm and architectures, routing algorithms for NoC architectures are presented and discussed at all abstraction levels, from the algorithmic level to actual implementation.  Coverage emphasizes the role played by the routing algorithm and is organized around key problems affecting current and next generation, many-core SoCs. A selection of routing algorithms is included, specifically designed to address key issues faced by designers in the ultra-deep sub-micron (UDSM) era, including performance improvement, power, energy, and thermal issues, fault tolerance and reliability.

Full Product Details

Author:   Maurizio Palesi ,  Masoud Daneshtalab
Publisher:   Springer-Verlag New York Inc.
Imprint:   Springer-Verlag New York Inc.
Edition:   2014 ed.
Dimensions:   Width: 15.50cm , Height: 2.40cm , Length: 23.50cm
Weight:   8.336kg
ISBN:  

9781461482734

ISBN 10:   1461482739
Pages:   410
Publication Date:   23 October 2013
Audience:   Professional and scholarly ,  Professional & Vocational
Format:   Hardback
Publisher's Status:   Active
Availability:   Manufactured on demand  
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Table of Contents

Part I Performance Improvement.- Basic Concepts on On-Chip Networks.- A Heuristic Framework for Designing and Exploring Deterministic Routing Algorithm for NoCs.- Run-Time Deadlock Detection.- The Abacus Turn Model.- Learning-based Routing Algorithms for on-Chip Networks.- Part II Multicast Communication.- Efficient and Deadlock-Free Tree-based Multicast Routing Method for Network-on-Chip.- Path-based Multicast Routing for 2D and 3D Mesh Networks.- Part III Fault Tolerance and Reliability.- Fault-Tolerant Routing Algorithms in Networks-on-Chip.- Reliable and Adaptive Algorithms for 2D and 3D Networks-on-Chip.

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