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OverviewSince register transfer level (RTL) design is less about being a bright engineer, and more about knowing the downstream implications of your work, this book explains the impact of design decisions taken that may give rise later in the product lifecycle to issues related to testability, data synchronization across clock domains, synthesizability, power consumption, routability, etc., all which are a function of the way the RTL was originally written. Readers will benefit from a highly practical approach to the fundamentals of these topics, and will be given clear guidance regarding necessary safeguards to observe during RTL design. Full Product DetailsAuthor: Sanjay Churiwala , Sapan Garg , Sapan GargPublisher: Springer-Verlag New York Inc. Imprint: Springer-Verlag New York Inc. Dimensions: Width: 15.50cm , Height: 1.20cm , Length: 23.50cm Weight: 0.489kg ISBN: 9781441992956ISBN 10: 1441992952 Pages: 182 Publication Date: 12 May 2011 Audience: Professional and scholarly , Professional & Vocational Format: Hardback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of ContentsReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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