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OverviewSince register transfer level (RTL) design is less about being a bright engineer, and more about knowing the downstream implications of your work, this book explains the impact of design decisions taken that may give rise later in the product lifecycle to issues related to testability, data synchronization across clock domains, synthesizability, power consumption, routability, etc., all which are a function of the way the RTL was originally written. Readers will benefit from a highly practical approach to the fundamentals of these topics, and will be given clear guidance regarding necessary safeguards to observe during RTL design. Full Product DetailsAuthor: Sanjay Churiwala , Sapan GargPublisher: Springer-Verlag New York Inc. Imprint: Springer-Verlag New York Inc. Edition: 2011 ed. Dimensions: Width: 15.50cm , Height: 1.10cm , Length: 23.50cm Weight: 0.454kg ISBN: 9781489995452ISBN 10: 1489995455 Pages: 182 Publication Date: 01 October 2014 Audience: Professional and scholarly , Professional & Vocational Format: Paperback Publisher's Status: Active Availability: Manufactured on demand  We will order this item for you from a manufactured on demand supplier. Table of ContentsReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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