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OverviewIntegrated circuit densities and operating speeds continue to rise at an exponential rate. Chips, however, cannot get larger and faster without a sharp decrease in power consumption beyond the current levels. Minimization of power consumption in VLSI chips has thus become an important design objective. In fact, with the explosive growth in demand for portable electronics and the usual push toward more complex functionality and higher performance, power consumption has in many cases become the limiting factor in satisfying the market demand. A new generation of power-conscious CAD tools are coming onto the market to help designers estimate, optimize and verify power consumption levels at most stages of the IC design process. These tools are especially prevalent at the register-transfer level and below. There is a great need for similar tools and capabilities at the behavioural and system levels of the design process. Many researchers and CAD tool developers are working on high-level power modelling and estimation, as well as power-constrained high-level synthesis and optimization. Techniques and tools alone are, however, insufficient to optimize VLSI circuit power dissipation, a consistent and convergent design methodology is also required. This book was written to address some of the key problems in power analysis and optimization early in the design process. In particular, it focuses on power macro-modelling based on regression analysis and power minimization through behavioural transformations, scheduling, resource assignment and hardware/software partitioning and mapping. What differentiates this book from other published work on the subject is the mathematical basis and formalism behind the algorithms and the optimality of these algorithms subject to the stated assumptions. Full Product DetailsAuthor: Jui-Ming Chang , Massoud PedramPublisher: Springer Imprint: Springer Edition: 1999 ed. Dimensions: Width: 15.50cm , Height: 1.20cm , Length: 23.50cm Weight: 1.000kg ISBN: 9780792385608ISBN 10: 0792385608 Pages: 167 Publication Date: 30 June 1999 Audience: General/trade , Professional and scholarly , Professional & Vocational Format: Hardback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of Contents1. Introduction.- 1.1 Low Power Design.- 1.2 Review of Behavioral Synthesis Techniques.- 1.3 Hardware/Software Co-design.- 1.4 Organization of the Book.- 2. Register Allocation and Binding.- 2.1 Introduction.- 2.2 Switching Activity Calculation.- 2.3 Register Binding with Minimum Power Dissipation.- 2.4 Experimental Results.- 2.5 Chapter Summary.- 3. Power-Optimal Module Allocation and Binding.- 3.1 Introduction.- 3.2 Terminology and Overview.- 3.3 Switching Activity Calculation.- 3.4 Module Binding with Minimum Power Dissipation.- 3.5 Multi-Commodity Flow Formulation.- 3.6 Experimental Results and Discussions.- 4. Multiple Supply Voltage Scheduling.- 4.1 Introduction.- 4.2 Related Problems.- 4.3 Energy-delay Curves.- 4.4 The Scheduling Algorithm.- 4.5 Functionally Pipelined Data-path.- 4.6 Experimental Results.- 4.7 Chapter Summary.- 5. Co-Design of Communicating Systems.- 5.1 Introduction.- 5.2 Related Work.- 5.3 Process Decomposition in a Task Graph.- 5.4 MILP Formulation for the Scheduling.- 5.5 Scheduling Using Dynamic Programming.- 5.6 Allocation and Binding.- 5.7 Experimental Results.- 5.8 Chapter Summary.- 6. Conclusion.- 6.1 Book Summary.- 6.2 Directions for Future Research.- References.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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