Free Delivery Over $100
|
|
|||
|
||||
OverviewIn the deep sub-micron regime, the power consumption has become one of the most important issues for competitive design of digital circuits. Due to dramatically increasing leakage currents, the power consumption does not take advantage of technology scaling as before. State-of-art power reduction techniques like the use of multiple supply and threshold voltages, transistor stack forcing and power gating are discussed with respect to implementation and power saving capability. Focus is given especially on technology dependencies, process variations and technology scaling. Design and implementation issues are discussed with respect to the trade-off between power reduction, performance degradation, and system level constraints. A complete top-down design flow is demonstrated for power gating techniques introducing new design methodologies for the switch sizing task and circuit blocks for data-retention and block activation. The leakage reduction ratio and the minimum power-down time are introduced as figures of merit to describe the power gating technique on system level and give a relation to physical circuit parameters. Power Management of Digital Circuits in Deep Sub-Micron CMOS Technologies mainly deals with circuit design but also addresses the interface between circuit and system level design on the one side and between circuit and physical design on the other side. Full Product DetailsAuthor: Stephan HenzlerPublisher: Springer-Verlag New York Inc. Imprint: Springer-Verlag New York Inc. Edition: 2007 ed. Volume: 25 Dimensions: Width: 15.50cm , Height: 1.20cm , Length: 23.50cm Weight: 1.030kg ISBN: 9781402050800ISBN 10: 1402050801 Pages: 186 Publication Date: 10 October 2006 Audience: Professional and scholarly , Professional & Vocational Format: Hardback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of ContentsTO LOW-POWER DIGITAL INTEGRATED CIRCUIT DESIGN.- LOGIC WITH MULTIPLE SUPPLY VOLTAGES.- LOGIC WITH MULTIPLE THRESHOLD VOLTAGES.- FORCING OF TRANSISTOR STACKS.- POWER GATING.- CONCLUSION.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
||||
