Power-Constrained Testing of VLSI Circuits: A Guide to the IEEE 1149.4 Test Standard

Author:   Nicola Nicolici ,  Bashir M. Al-Hashimi
Publisher:   Springer-Verlag New York Inc.
Edition:   2003 ed.
Volume:   22B
ISBN:  

9781402072352


Pages:   178
Publication Date:   28 February 2003
Format:   Hardback
Availability:   In Print   Availability explained
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Power-Constrained Testing of VLSI Circuits: A Guide to the IEEE 1149.4 Test Standard


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Overview

Minimization of power dissipation in very large scale integrated (VLSI) circuits is important to improve reliability and reduce packaging costs. While many techniques have investigated power minimization during the functional (normal) mode of operation, it is important to examine the power dissipation during the test circuit activity is substantially higher during test than during functional operation. For example, during the execution of built-in self-test (BIST) in-field sessions, excessive power dissipation can decrease the reliability of the circuit under test due to higher temperature and current density. This text focuses on techniques for minimizing power dissipation during test application at logic and register-transfer levels of abstraction of the VLSI design flow. The first part of this book surveys the existing techniques for power constrained testing of VLSI circuits. In the second part, several test automation techniques for reducing power in scan-based sequential circuits and BIST data paths are presented.

Full Product Details

Author:   Nicola Nicolici ,  Bashir M. Al-Hashimi
Publisher:   Springer-Verlag New York Inc.
Imprint:   Springer-Verlag New York Inc.
Edition:   2003 ed.
Volume:   22B
Dimensions:   Width: 21.00cm , Height: 1.20cm , Length: 29.70cm
Weight:   0.990kg
ISBN:  

9781402072352


ISBN 10:   140207235
Pages:   178
Publication Date:   28 February 2003
Audience:   College/higher education ,  Professional and scholarly ,  Undergraduate ,  Postgraduate, Research & Scholarly
Format:   Hardback
Publisher's Status:   Active
Availability:   In Print   Availability explained
This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us.

Table of Contents

Design and Test of Digital Integrated Circuits.- Power Dissipation During Test.- Approaches to Handle Test Power.- Power Minimization Based on Best Primary Input Change Time.- Test Power Minimization Using Multiple Scan Chains.- Power-conscious Test Synthesis and Scheduling.- Power Profile Manipulation.- Conclusion.

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