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OverviewThis book contributes the thoroughly refereed post-proceedings of the Third International Workshop on Power-Aware Computer Systems, PACS 2003, held in San Diego, CA, USA in December 2003.The 14 revised full papers presented were carefully selected during two rounds of reviewing and improvement from 43 submissions. The papers span a wide spectrum of topics in power-aware systems; they are organized in topical sections on compilers, embedded systems, microarchitectures, and cache and memory systems. Full Product DetailsAuthor: Babak Falsafi , T. N. VijaykumarPublisher: Springer-Verlag Berlin and Heidelberg GmbH & Co. KG Imprint: Springer-Verlag Berlin and Heidelberg GmbH & Co. K Edition: 2005 ed. Volume: 3164 Dimensions: Width: 15.50cm , Height: 1.20cm , Length: 23.50cm Weight: 0.730kg ISBN: 9783540240310ISBN 10: 3540240314 Pages: 215 Publication Date: 17 December 2004 Audience: Professional and scholarly , Professional & Vocational Format: Paperback Publisher's Status: Active Availability: In Print This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of ContentsCompilers.- Runtime Biased Pointer Reuse Analysis and Its Application to Energy Efficiency.- Inter-program Compilation for Disk Energy Reduction.- Embedded Systems.- Energy Consumption in Mobile Devices: Why Future Systems Need Requirements-Aware Energy Scale-Down.- Efficient Scratchpad Allocation Algorithms for Energy Constrained Embedded Systems.- Online Prediction of Battery Lifetime for Embedded and Mobile Devices.- Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture.- Heterogeneous Wireless Network Management.- Microarchitectural Techniques.- Look It Up or Do the Math : An Energy, Area, and Timing Analysis of Instruction Reuse and Memoization.- CPU Packing for Multiprocessor Power Reduction.- Exploring the Potential of Architecture-Level Power Optimizations.- Coupled Power and Thermal Simulation with Active Cooling.- Cache and Memory Systems.- The Synergy Between Power-Aware Memory Systems and Processor Voltage Scaling.- Hot-and-Cold: Using Criticality in the Design of Energy-Efficient Caches.- PARROT: Power Awareness Through Selective Dynamically Optimized Traces.ReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |