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OverviewThis concise volume contains the key papers presented during the International NATO Advanced Research Workshop on Silicon on Insulator device technologies. The authors have moved beyond reporting the current state of the technology to explore wider issues, from the economic aspects incorporating SOI and related materials into circuits and systems to consideration of low temperature electronics, quantum devices and MEMS. Full Product DetailsAuthor: Peter L. F. Hemment , Vladimir S. Lysenko , Alexei N. NazarovPublisher: Springer Imprint: Springer Edition: Softcover reprint of the original 1st ed. 2000 Volume: 73 Dimensions: Width: 16.00cm , Height: 1.90cm , Length: 24.00cm Weight: 1.140kg ISBN: 9780792361176ISBN 10: 0792361172 Pages: 344 Publication Date: 31 December 1999 Audience: College/higher education , Professional and scholarly , Postgraduate, Research & Scholarly , Professional & Vocational Format: Paperback Publisher's Status: Active Availability: In Print  This item will be ordered in for you from one of our suppliers. Upon receipt, we will promptly dispatch it out to you. For in store availability, please contact us. Table of ContentsPreface. Committee Members. Invited Speakers. Workshop Photographs. Section 1: Innovations in Materials Technologies. 1.1. SMART-CUT® Technology: Basic Mechanisms and Applications; M. Bruel. 1.2. Polish Stop Technology for Silicon on Silicide on Insulator Structures; H.S. Gamble. 1.3. Homoepitaxy on Porous Silicon with a Buries Oxide Layer; Full-Wafer Scale SOI; S.I. Romanov, et al. 1.4. Structural and Electrical Properties of Silicon on Isolator Structures Manufactured on FZ- and CZ-Silicon by SMART-CUT Technology; V.P. Popov, et al. 1.5. Development of Linear Sequential Lateral Solidification Technique to Fabricate Quasi-Single-Crystal Super-Thin Si Films for High-Performance Thin Film Transistor Devices; A.B. Limanov, et al. Section 2: Economics and Innovation Applications. 2.1. Low Temperature Polysilicon Technology: A Low Cost SOI Technology? F. Plais, et al. 2.2. A Novel Low Cost Process for the Production of Semiconductor Polycrystalline Silicon from Recycled Industrial Waste; B.N. Mukashev, et al. 2.3. Tetrahedrally Bonded Amorphous Carbon for Electronic Applications; W.I. Milne. 2.4. Diamond Based Silicon-on-Insulator Materials and Devices; S. Bengtsson, M. Bergh. 2.5. Low-Temperature Processing of Crystalline Si Films on Glass for Electronic Applications; R.B. Bergmann, et al. 2.6. beta-SiC on SiO2 Formed by Ion Implantation and Bonding for Micromechanics Applications; C. Serre, et al. 2.7. Laser Recrystallized Polysilicon Layers for Sensor Applications: Electrical Piezoresistive Characterization; A.A. Druzhinin, et al. Section 3: CharacterisationMethods for SOI. 3.1. Optical Spectroscopy of SOI Materials; A. Pérez-Rodríguez, et al. 3.2. Computer Simulation of Oxygen Redistribution in SOI Structures; V.G. Litovchenko, A.A. Efremov. 3.3. Electrical Instabilities in Silicon-on-Insulator Structures and Devices During Voltage and Temperature Stressing; A.N. Nazarov, et al. 3.4. Hydrogen as a Diagnostic Tool in Analysing SOI Structures; A. Boutry-Forveille, et al. 3.5. Back Gate Voltage Influence on the LDD SOI NMOSFET Series Resistance Extraction from 150 to 300 K; A.S. Nicolett, et al. 3.6. Characterization of Porous Silicon Layers Containing a Buried Oxide Layer; S.I. Romanov, et al. 3.7. Total-Dose Radiation Response of Multilayer Buried Insulators; A.N. Rudenko, et al. 3.8. Recombination Current in Fully-Depleted SOI Diodes: Compact Model and Lifetime Extraction; T. Ernst, et al. 3.9. Investigation of the Structural and Chemical Properties of SOI Materials by Ellipsometry; L.A. Zabashta, et al. 3.10. Experimental Investigation and Modeling of Coplanar Transmission Lines on SOI Technologies for RF Applications; J. Lescot, et al. Section 4: Perspectives for SOI Structures and Devices. 4.1. Perspectives of Silicon-on-Insulator Technologies for Cryogenic Electronics; C. Claeys, et al. 4.2. SOI CMOS for High-Temperature Applications; J.P. Colinge. 4.3. Quantum Effect Devices on SOI Substrates with an Ultrathin Silicon Layer; Y. Omura. 4.4. Wafer Bonding for Micro-ElectroMechanical Systems (MEMS); C.A. Colinge. 4.5. A ComReviewsAuthor InformationTab Content 6Author Website:Countries AvailableAll regions |
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