Overview

As VLSI technology moves to the nanometer scale for transistor feature sizes, the impact of manufacturing imperfections result in large variations in the circuit performance. Traditional CAD tools are not well-equipped to handle this scenario, since they do not model this statistical nature of the circuit parameters and performances, or if they do, the existing techniques tend to be over-simplified or intractably slow. Novel Algorithms for Fast Statistical Analysis of Scaled Circuits draws upon ideas for attacking parallel problems in other technical fields, such as computational finance, machine learning and actuarial risk, and synthesizes them with innovative attacks for the problem domain of integrated circuits. The result is a set of novel solutions to problems of efficient statistical analysis of circuits in the nanometer regime.

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<p>The Statistical Blockade method proposed by Singhee and Rutenbar will make a significant impact on the design of next-generation digital integrated circuits. It has the potential to dramatically reduce simulation time compared to a traditional Monte Carlo approach. Their award winning work is well received by industry and has influenced research directions in academia.<br>- Prof. Anantha Chandrakasan, MIT

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